← Back to Patent Explorer
EP0242634A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Byte count handling in serial channel extender with buffering for data pre-fetch

Assignee: International Business Machines Corp
•
Filing: 1987-03-27
•
Granted: —
•
Expires: 2007-03-27
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A channel subsystem is provided with a conventional serial extender link that causes communications between a channel (12) and a control unit (18) to be delayed by the additional time to transmit a message in one direction and to transmit an acknowledgement in the other direction, and it has a buffer and associated components (called a channel outboard box 22) that are used for prefetching data from processor memory or from a peripheral device without waiting for the acknowledgement routines that are commonly used on both an interlocked data transfer and a non-interlocked transfer (called data streaming). A system of counters and other components and associated operations is provided that maintains the correct byte count that would otherwise be maintained in a system without the prefetch buffer and with only a short serial link. A system of count and status frames is provided for sending byte count and other status information between the channel and the outboard box.

Inventors

  • 👤 Salvatore Anthony Calta
  • 👤 Thomas Anthony Gregg
  • 👤 Leon Skarshinski
  • 👤 Richard Strangwayes

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-28 14:01
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/4226; G06F13/10; G06F13/12; G06F13/122; G06F13/14; G06F13/20; G06F13/28

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 226 words
A data processing system having apparatus (22) for interconnecting a parallel bus (26, 27) of a control unit (18) and , serial link (14) of a channel, comprising, means (47) for storing a byte count, a buffer memory (39), a parallel bus (27m) for data to be stored in the buffer memory and a parallel bus (36) for data fetched from the buffer memory, means (30b) connected between said parallel busses of said buffer and said parallel bus of the control unit for handling read and write operations according to a predetermined protocol, means (28,29) for sending and receiving frames on the serial link, said sending and receiving means including means for converting between a serial format of incoming or outgoing frames on the serial link and a parallel format of the control unit parallel bus and the buffer memory, the frame format including a data field and a command field, the command field holding a binary code identifying the contents of the data field, a first command code identifying a data field containing a byte count for a data transfer and a second command code identifying a data field containing data for an interlocked read data transfer, and means (37) for decoding the command field of an incoming frame and means (41) for transferring a byte count data field to the byte count storing means.
Claim 2
Dependent Claim 226 words
A data processing system having apparatus (22) for interconnecting a parallel bus (26, 27) of a control unit (18) and , serial link (14) of a channel, comprising, means (47) for storing a byte count, a buffer memory (39), a parallel bus (27m) for data to be stored in the buffer memory and a parallel bus (36) for data fetched from the buffer memory, means (30b) connected between said parallel busses of said buffer and said parallel bus of the control unit for handling read and write operations according to a predetermined protocol, means (28,29) for sending and receiving frames on the serial link, said sending and receiving means including means for converting between a serial format of incoming or outgoing frames on the serial link and a parallel format of the control unit parallel bus and the buffer memory, the frame format including a data field and a command field, the command field holding a binary code identifying the contents of the data field, a first command code identifying a data field containing a byte count for a data transfer and a second command code identifying a data field containing data for an interlocked read data transfer, and means (37) for decoding the command field of an incoming frame and means (41) for transferring a byte count data field to the byte count storing means.
Claim 3
Dependent Claim 49 words
The data processing system of claim 1 including means for decoding a frame designating whether a forthcoming operation is to use said buffer and means for transmitting data between said control unit and said channel through said buffer or bypassing said buffer according to information in said designating frame.
Claim 4
Dependent Claim 59 words
The data processing system of claim 2 wherein said designating frame contains to a third command code signifying that the data field contains information for the apparatus, and said means for transmitting data between said control unit and said channel includes means responsive to information in said data field for transmitting data through said buffer or bypassing said buffer.
Claim 5
Dependent Claim 72 words
The data processing system of claim 2 including means for updating said means for storing a byte count when a byte is transferred from said buffer to said parallel bus of said control unit and means for forming a serial frame containing a third command code identifying that the data field of the frame contains a byte count and means for sending the byte count to the channel during a write operation.
Claim 6
Dependent Claim 28 words
The data processing system of claim 2 wherein said apparatus includes means for calculating the residual count and sending it to the channel in a residual count frame.
Claim 7
Dependent Claim 36 words
The data processing system of claim 5 including means for forming a frame signaling to the channel that the apparatus sent to the control unit a signal (Command Out) to end a read or write operation.
Claim 8
Dependent Claim 36 words
The data processing system of claim 5 including means for forming a frame signaling to the channel that more bytes were received and acknowledged that required by the count sent to the apparatus by the channel.
Claim 9
Dependent Claim 57 words
The data processing system of claim 3 wherein said frame format includes a fourth command code identifying a data transfer in a non-interlocked mode (data streaming) and wherein said apparatus includes means operable on a non-interlocked read operation for transferring bytes on said parallel bus to said buffer, whereby the byte count is handled by said apparatus.
Claim 10
Dependent Claim 30 words
The data processing system of claim 1 wherein said channel includes a frame counter and a buffer and means for updating said frame counter as bytes are transferred and acknowledged.
Claim 11
Dependent Claim 42 words
The data processing system of claim 5 wherein said channel includes a separate channel front end including means for communicating with the channel on a parallel bus and means for communicating with said apparatus on the serial link and said frame counter.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag