EP0242595A2
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Error detection using variable field parity checking
Assignee: International Business Machines Corp
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Filing: 1987-03-20
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Granted: —
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Expires: 2007-03-20
Abstract
Abstract A variable number of parity bits or error correction code per word is used to increase error detection for words having the extra parity bits in a control store. Since some words do not utilize all the architected space available for words, extra parity bits are generated at development time for such words and stored with the words. A decoder 10 identifies the location and number of parity bits. Parity checking against the extra parity bits is then performed on different groups of bits in the word. This provides an inexpensive means of increasing error detection with minimal hardware cost.
Inventors
- 👤 Bruce Ralph Petz
- 👤 Richard Phillip Rieger
- 👤 Andrew Dale Walls
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 23:55
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1076
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
82 words
A parity checker for a memory storing variable length multibit words (12) having a variable number of parity bits, the checker characterized in that it comprises: word decode means (14) for decoding said variable length words to identify the parity bits contained therein; and parity checking means coupled to said word decode means for checking the parity of selected bits in said words against the identified parity bits as a function of the variable number of parity bits contained in each word.
Claim 2
Dependent Claim
82 words
A parity checker for a memory storing variable length multibit words (12) having a variable number of parity bits, the checker characterized in that it comprises: word decode means (14) for decoding said variable length words to identify the parity bits contained therein; and parity checking means coupled to said word decode means for checking the parity of selected bits in said words against the identified parity bits as a function of the variable number of parity bits contained in each word.
Claim 3
Dependent Claim
36 words
The parity checker of claim 1 characterized in that said parity bits comprise both fixed parity bits (P1, P2, P3) common to all types of words, and extra parity bits dependent upon the types of words.
Claim 4
Dependent Claim
30 words
The parity checker of claim 1 or 2 characterized in that the number and location of parity bits is a function of the type of word containing the parity bits.
Claim 5
Dependent Claim
33 words
The parity checker of claim 3 characterized in that each word comprises a decode field used by said decode means to identify the type of word, and the locations of the parity bits.
Claim 6
Dependent Claim
41 words
The parity checker of claim 4 characterized in that each word comprises a plurality of subfields, and the location of at least one parity bit in selected words is a function of the bit value in one or more such subfields.
Claim 7
Dependent Claim
33 words
The parity checker of anyone of claims 1-5 characterized in that the words are stored in a plurality of fast access memory modules, the bits of each word being stored on different modules.
Claim 8
Dependent Claim
33 words
The parity checker of claim 6 characterized in that the bits of words are divided in groups for parity checking purposes, and each module contains at least one bit from one selected group.
Claim 9
Dependent Claim
36 words
The parity checker of claim 7 characterized in that the bits in each group are spread out over the modules such that a failure of one module will affect the parity of more than one group.
Claim 10
Dependent Claim
47 words
The parity checker of claim 8 characterized in that the parity bits comprise both fixed and extra parity bits, and wherein the fixed parity bits correspond to the parity of combinations of groups of bits, and selected extra parity bits correspond to the parity of selected groups.
Claim 11
Independent Claim
81 words
A method of checking parity of multibit words containing parity bits in variable locations, characterized in that it comprises the steps of: a) decoding the words to identify the variable location of at least one parity bit contained therein; b) generating parity for at least one group of bits to be parity checked; and c) checking the parity of the at least one group of bits against the corresponding at least one parity bit identified to detect errors in the word.
Claim 12
Independent Claim
81 words
A method of checking parity of multibit words containing parity bits in variable locations, characterized in that it comprises the steps of: a) decoding the words to identify the variable location of at least one parity bit contained therein; b) generating parity for at least one group of bits to be parity checked; and c) checking the parity of the at least one group of bits against the corresponding at least one parity bit identified to detect errors in the word.
References Cited (Backward Citations)
No citation records indexed.
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