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EP0242093A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Resynchronization of serial data blocks

Assignee: HP Inc
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Filing: 1987-04-03
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Granted: —
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Expires: 2007-04-03
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Abstract

Abstract A method and apparatus for re-synchronization of serial data blocks (13,17) utilizing recorded re-synchronizing signals (15a,15b,...,19a,19b,....) separating sub-blocks (13a,­13b,...,17a,17b,....) of data is provided. Use of the re-­synchronization signals (15a,15b,...,19a,19b,....) in combination with error correction codes allows the recovery of data lost due to a signal drop-out even when clock synchronization is also lost. The optimum re-synchronization mark comprises a unique key (40) having a header (44) of two b bits preceding the key and a trailer (42) of b bits appended to the key where b is the maximum correctable number of bits slipped that the clock can be out of synchronization with the beginning of a data sub-block.

Inventors

  • 👤 Kel D. Winters
  • 👤 Bruce F. Spenner
  • 👤 David J. Bromley
  • 👤 Richard A. Baugh

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-08 16:16
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/12; G11B20/1201; G11B20/1207; G11B20/1209; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 282 words
Electronic apparatus, such as a videotape recorder or the like utilizing a data error correction code, for recording and reproducing data information words, said electronic apparatus comprising: coding means (6) for coding and forming a block (13, 17) of a plurality of said data information words, first means (6) for forming and adding a plurality of error check bits to each of said data information words, second means (6) for forming each of said data infor­mation words and error check bits in said block (13,17) into a plurality of sub-blocks (13a,13b,...,17a,17b,....), each of said sub-blocks (13a,13b,...,17a,17b,....) having a predetermined number of bits, said predetermined number of bits being no greater than the number of bits correctable by said error correc­tion code, characterized by third means (8) for forming a re-synchronization word (15a,15b,...,19a,19b,....) having a predetermined number of bits arranged in a recognizable unique bit pattern, said re-synchroni­zation word (15a,15b,...,19a,19b,....) indicative of the position of the beginning of a sub-block (13a,13b,...,17a,17b,....), recording means (12) for recording one of said plural ity of sub-blocks (13a,13b,...,17a,17b,....), then recording said re-synchronization word (15a,15b,...,19a,19b,....) and repeating such recording steps until all of said data information words and error check bits in said block (13,17) are recorded, reading means (12) for reading said recorded block (13,17) of data information words and error check bits, detecting means (12) for detecting said re-synchroniza­tion word (15a,15b,...,19a,19b,....), means (8) responsive to said detected re-synchroniza­tion word (15a,15b,...,19a,19b,....) for synchronizing a read clock with said beginning of the succeeding sub-block (13a,­13b,...,17a,17b,....), and decoding means (6) for decoding said plurality of sub-­blocks (13a,13b,...,17a,17b,....), said means (6) for decoding responsive to said plurality of error check bits for error detec­tion and correction in said information words.
Claim 2
Dependent Claim 282 words
Electronic apparatus, such as a videotape recorder or the like utilizing a data error correction code, for recording and reproducing data information words, said electronic apparatus comprising: coding means (6) for coding and forming a block (13, 17) of a plurality of said data information words, first means (6) for forming and adding a plurality of error check bits to each of said data information words, second means (6) for forming each of said data infor­mation words and error check bits in said block (13,17) into a plurality of sub-blocks (13a,13b,...,17a,17b,....), each of said sub-blocks (13a,13b,...,17a,17b,....) having a predetermined number of bits, said predetermined number of bits being no greater than the number of bits correctable by said error correc­tion code, characterized by third means (8) for forming a re-synchronization word (15a,15b,...,19a,19b,....) having a predetermined number of bits arranged in a recognizable unique bit pattern, said re-synchroni­zation word (15a,15b,...,19a,19b,....) indicative of the position of the beginning of a sub-block (13a,13b,...,17a,17b,....), recording means (12) for recording one of said plural ity of sub-blocks (13a,13b,...,17a,17b,....), then recording said re-synchronization word (15a,15b,...,19a,19b,....) and repeating such recording steps until all of said data information words and error check bits in said block (13,17) are recorded, reading means (12) for reading said recorded block (13,17) of data information words and error check bits, detecting means (12) for detecting said re-synchroniza­tion word (15a,15b,...,19a,19b,....), means (8) responsive to said detected re-synchroniza­tion word (15a,15b,...,19a,19b,....) for synchronizing a read clock with said beginning of the succeeding sub-block (13a,­13b,...,17a,17b,....), and decoding means (6) for decoding said plurality of sub-­blocks (13a,13b,...,17a,17b,....), said means (6) for decoding responsive to said plurality of error check bits for error detec­tion and correction in said information words.
Claim 3
Dependent Claim 57 words
Electronic apparatus according to claim 1 charac­terized in that said second means (6) comprises means for inter­leaving each of said data information words and error check bits in said block (13,17) into a plurality of interleaved sub-blocks (13a,13b,...,17a,17b,....), each of said interleaved sub-blocks (13a,13b,...,17a,17b,....) having no more than lambda bits where lambda is the degree of interleaving.
Claim 4
Dependent Claim 46 words
Electronic apparatus according to Claim 1 or 2 characterized in that said resynchronization word (15a,­15b,...,19a,19b,....) includes a predetermined number of bits arranged in a first recognizable bit pattern (44) preceding said unique bit pattern and a second recognizable bit pattern (42) following said unique bit pattern.
Claim 5
Dependent Claim 58 words
Electronic apparatus according to claim 3 charac­terized in that said first recognizable bit pattern (44) is 2 b bits in length and said second recognizable bit pattern (42) is b bits in length where b is the maximum correctable number of bits that said read clock may be out of synchronization with the beginning of the succeeding sub-block.
Claim 6
Independent Claim 146 words
A method of re-synchronizing a read clock with the beginning of a data sub-block recorded in a suitable media, said method comprising the steps of: formatting a data stream in blocks (13,17) of a plu­rality of said data sub-blocks (13a,13b,...,17a,17b,....), having a predetermined number of bits, characterized by the steps of forming a re-synchronization signal (15a,15b,...,­19a,19b,....) having a predetermined number of bits arranged in a recognizable unique bit pattern, indicative of the position of the beginning of said data sub-blocks (13a,13b,...,­ 17a, 17b, ....), recording one of said plurality of data sub-blocks (13a,13b,...,17a,17b,....) and then recording said re-synchroni­zation signal (15a,15b,...,19a,19b,....) and repeating such recording steps until all of said plurality of data sub-blocks (13a,13b,...,17a,17b,....) in each block (13,17) are recorded, detecting said re-synchronization signal, and synchronizing said read clock with the beginning of the next succeeding data sub-block (13a,13b,...,17a,17b,....) in response to said detected re-synchronization signal.
Claim 7
Independent Claim 146 words
A method of re-synchronizing a read clock with the beginning of a data sub-block recorded in a suitable media, said method comprising the steps of: formatting a data stream in blocks (13,17) of a plu­rality of said data sub-blocks (13a,13b,...,17a,17b,....), having a predetermined number of bits, characterized by the steps of forming a re-synchronization signal (15a,15b,...,­19a,19b,....) having a predetermined number of bits arranged in a recognizable unique bit pattern, indicative of the position of the beginning of said data sub-blocks (13a,13b,...,­ 17a, 17b, ....), recording one of said plurality of data sub-blocks (13a,13b,...,17a,17b,....) and then recording said re-synchroni­zation signal (15a,15b,...,19a,19b,....) and repeating such recording steps until all of said plurality of data sub-blocks (13a,13b,...,17a,17b,....) in each block (13,17) are recorded, detecting said re-synchronization signal, and synchronizing said read clock with the beginning of the next succeeding data sub-block (13a,13b,...,17a,17b,....) in response to said detected re-synchronization signal.
Claim 8
Dependent Claim 64 words
The method according to claim 5 characterized in that said step of detecting said re-synchronization signal (15a,15b,...,19a,19b,....) includes beginning a search for said re-synchronization signal (15a,15b,...,19a,19b,....) b bits prior to the anticipated beginning of said re-synchronization signal where b is the maximum correctable number of bits that said read clock may be out of synchronization with said beginning of the next succeeding data sub-block.
Claim 9
Dependent Claim 47 words
The method according to claim 5 or 6 characterized in that said re-synchronization signal (15a,15b,...,19a,19b,....) includes a predetermined number of bits arranged in a first recognizable bit pattern (44) preceding said unique bit pattern and in a second recognizable bit pattern (42) following said unique bit pattern.
Claim 10
Dependent Claim 33 words
The method according to claim 7 characterized in that said first recognizable bit pattern (44) is 2 b bits in length and said second recognizable bit pattern (42) is b bits in length.

References Cited (Backward Citations)

US3641534A Cited
EP0133790A1 Cited
EP0166785A1 Cited
EP0164746A2 Cited

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