Circuit board for on-line insertion in computer system

Claim 2

A circuit board for on-line insertion in a computer system of the type having a plurality of clock lines including a clock line for the board, a bus and an INIT line carrying an INIT signal, comprising: means for stopping traffic on the bus during insertion of the board; means for decoupling the clock line for the board from the other clock lines; and means for providing fully distributed synchronization of the INIT signal.

Claim 3

A circuit board according to claim 1, including a parameter controller and wherein the means for decoupling the clock line includes a clock driver having its input connected to a terminal for receiving a clock signal from the clock line for the board and its output connected to the parameter controller.

Claim 4

A circuit board according to claim 2, wherein the parameter controller receives the INIT signal.

Claim 5

A circuit board according to claim 2, including a synchronization logic circuit having one input connected to the output of the parameter controller and having another input connected to a terminal for receiving a phase clock signal from one of the plurality of clock lines.

Claim 6

A circuit board according to claim 5, wherein the parameter controller generates a local INIT signal in response to receiving a system INIT signal.

Claim 7

A circuit board according to claim 1, wherein the means for decoupling the clock line includes a clock driver on the board having its input connected to a terminal for receiving a system clock signal from the clock line for the board and decoupling the system clock line from the plurality of clock lines.

Claim 8

A circuit board according to claim 1, wherein the means for providing fully distributed synchronization of the INIT signal includes: a parameter controller receiving an INIT signal from the INIT line and a system clock signal from the clock line; and a synchronization logic circuit receiving a local INIT signal from the parameter controller and receiving a phase clock signal from one of the plurality of clock lines and generating local board INIT signals.

Claim 9

A circuit board according to claim 9, wherein the synchronization logic circuit includes: a logic gate receiving the local INIT signal from the parameter controller and producing an output in response to receiving the local INIT signal from the parameter controller; a first flip-flop receiving the gate output at its input and being clocked by the phase clock signal; a second flip-flop receiving the first flip-flop output and being clocked by the phase clock signal and producing one of the local board INIT signals; and a third flip-flop receiving the first flip-flop output and being clocked by the phase clock signal and producing one of the local board INIT signals.

Claim 10

A circuit board according to claim 10, wherein the first flip-flop synchronizes the second and third flip-flops.

Claim 11

A circuit board according to claim 10, including a master component connected to the output of the second flip-flop and a checker component connected to the output of the third flip-flop.

Claim 12

A circuit board according to claim 10, including: a resistor having one end connected to a source of positive voltage, and a capacitor having one end grounded and the other end connected to the free end of the resistor, said gate having its input connected to the junction of the resistor and capacitor, said resistor and capacitor holding the output of the gate at a defined state for a preselected time.

Claim 13

A circuit board according to claim 1, wherein the means for stopping bus traffic on the bus during insertion of the board includes staggered terminals.

Claim 14

A circuit board according to claim 1 wherein the computer system has a backplane with a plurality of terminals and the means for stopping traffic on the bus during insertion of the board includes: a power terminal, a ground terminal and an output terminal each extending a distance A from the board; at least one bus terminal extending a distance B from the board with distance A being greater than distance B; a gate connected to the ground and power terminals and having its output connected to the output terminal and having its input connected to the ground and power terminals via a circuit which during board insertion applies the voltage potential of the ground terminal for a preselected time causing the gate output to go low thereby interrupting bus traffic and thereafter applies to the potential of the power terminal causing the gate output to go high thereby resuming bus traffic.