Memory device with reduced power consumption

Claim 2

A memory device as claimed in claim I in which said access circuit means comprises a row address buffer circuit supplied with the row address from said input terminal means, a word line driver circuit supplied with output signals of said row address buffer circuit and responsive to said disable signal for setting said selected one of the word lines to the first level, a column address buffer circuit supplied with the column address from said input terminal means and responsive to said disable signal, and a bit line driver circuit supplied with output signals of said column address buffer circuit for setting said selected one of the bit lines to the second level, said first level being a low level and said second level being a high level.

Claim 3

A memory device as claimed in claim 2 in which said word line driver circuit comprises a plurality of NAND circuits each supplied with the output signals of said row address buffer circuit and responsive to said disable signal for supplying output signals to corresponding ones of said plurality of word lines.

Claim 4

A memory device as claimed in claim 2 in which said column address buffer circuit comprises with respect to each bit of the column address a first tri-state buffer supplied with one bit of the column address and a second tri-state buffer supplied with an output signal of said first tri-state buffer, said first and second tri-state buffers being responsive to said disable signal and carrying out an inverting operation during a low-level period of said disable signal and having a high impedance at outputs thereof during a high-level period of said disable signal, said bit line driver circuit receiving output signals of said first and second tri-state buffers as the output signals of said column address buffer circuit.

Claim 5

A memory device as claimed in claim I in which said comparing circuit means prevents a current from flowing through all of the word lines and bit lines when the memory device is disabled by said disable signal and causes the current to flow through said comparing circuit means, said current being limited by said constant current source.

Claim 6

A memory device as claimed in claim I in which said comparing circuit means comprises a plurality of first transistors having bases coupled to corresponding ones of said plurality of bit lines and supplied with a power source voltage via respective resistors, said first transistors having collectors coupled in common and having emitters coupled in common, a second transistor having a collector supplied with the power source voltage via a resistor and having a base supplied with said reference level, and said constant current circuit coupled to the emitters of said first and second transistors for limiting emitter currents of said first transistors to a constant value, said output circuit means receiving the information read out by said comparing circuit means from the collector of said second transistor.

Claim 7

A memory device as claimed in claim I in which said output circuit means comprises a tri-state buffer responsive to said disable signal for inverting the information read out by said comparing circuit means during a low-level period of said disable signal and for making the impedance at an output of said tri-state buffer during a high-level period of said disable signal.

Claim 8

A memory device as claimed in claim I in which said control means comprises an inverter supplied with said disable signal for supplying an inverted disable signal to said access circuit means and to said output circuit means.

Claim 9

A memory device comprising: a memory cell array comprising a plurality of memory cells in a matrix arrangement, said plurality of memory cells being coupled to word lines and bit lines; input terminal means supplied with a row address and a column address for designating a memory cell within said memory cell array; access circuit means for setting a selected one of the word lines to a first level responsive to the row address from said input terminal means and for setting a selected one of the bit lines to a second level responsive to the column address from said input terminal means so as to designate one of said plurality of memory cells within said memory cell array by the row and column addresses; comparing circuit means driven by a constant current source thereof for reading out a stored information from said designated memory cell via the bit lines by comparing a bit line level with a reference level; output circuit means for outputting the information read out by the comparing circuit means; and control circuit means responsive to a disable signal for setting all of the word lines and bit lines to a high level and setting the impedance at an output of said output circuit means to a high impedance when the memory device is disabled by said disable signal.

Claim 10

A memory device comprising: a memory cell array-comprising a plurality of memory cells in a matrix arrangement, said plurality of memory cells being coupled to word lines and bit lines; input terminal means supplied with a row address and a column address for designating a memory cell within said memory cell array; access circuit means for setting a selected one of the word lines to a first level responsive to the row address from said input terminal means and for setting a selected one of the bit lines to a second level responsive to the column address from said input terminal means so as to designate one of said plurality of memory cells within said memory cell array by the row and column addresses ; comparing circuit means .driven by a constant current source thereof for reading out a stored information from said designated memory cell via the bit lines by comparing a bit line level with a reference level; output circuit means for outputting the information read out by the comparing circuit means; and control circuit means responsive to a disable signal for setting all of the word lines to a high level, setting all of the. bit lines to have a high impedance and setting the impedance at an output of said output circuit means to a high impedance when the memory device is disabled by said disable signal.

Claim 11

II. A memory device comprising: a memory cell array comprising a plurality of memory cells in a matrix arrangement, said plurality of memory cells being coupled to word lines and bit lines; input terminal means supplied with a row address and a column address for designating a memory cell within said memory cell array; access circuit means for setting a selected one of the word lines to a first level responsive to the row address from said input terminal means and for setting a selected one of the bit lines to a second level responsive to the column address from said input terminal means so as to designate one of said plurality of memory cells within said memory cell array by the row and column addresses; comparing circuit means driven by a constant current source thereof for reading out a stored information from said designated memory cell via the bit lines by comparing a bit line level with a reference level; output circuit means for outputting the information read out by the comparing circuit means; and control circuit means responsive to a disable signal for setting all of the word lines to have a high impedance, setting all of the bit lines to a high level and setting the impedance at an output of said output circuit means to a high impedance when the memory device is disabled by said disable signal.