Automatic telecommunication switching system

Claim 2

An automatic telecommunication switching system, in which intelligence is handled in packet manner, in which the system includes a plural-stage switching network each stage of which includes a plurality of co-ordinate matrices each of which interconnects a plurality of inlets and outlets, in which each said matrix has its own memory and processing means, so that control of the system is at least partly distributed, in which each intelligence packet on arriving at a said matrix is routed into that matrix's memory means and its address information examined by the matrix's processing means to ascertain how the packet is to be routed, and in which in response to said examination the processing means at a matrix routes a said packet to an outlet of that matrix appropriate to the packets' address information, so that a packet is progressed through the switching network in a stage-by-stage manner under the control of the processing means of the appropriate matrices.

Claim 3

A system as claimed in claim 1, and in which the connections of subscriber's lines, trunks and facilities circuits to the network are each made via interface modules which, at least in the cases of the lines and trunks, include processing means.

Claim 4

A system as claimed in claim 1, and in which interprocessor communications between module interfaces and/or the processing means at the matrices is effected over the same physical path as that used for the intelligence.

Claim 5

An automatic telecommunication switching system in which intelligence is handled in packet manner, in which the system includes a plural-stage folded switching network with the terminals served by the system connected to one side of the network, in which each connection between two of said terminals is set up via two half-connections one of which extends into the network from said one side and the other of which comes out of the network to said one side, in which each stage of the switching network includes a number of co-ordinate matrices each including a number of semiconductor cross-points, each such matrix interconnecting a plurality of matrix inlets and matrix outlets, in which each said switching matrix has its own memory means and its own processing means so that control of the system is at least partly distributed, in which when an intelligence packet traversing the network between two of said terminals arrives at a said matrix that packet is routed into that matrix's memory means and its address information is examined by that matrix's processing means to ascertain how the packet is to be routed, in which in response to said examination the processing means at a said matrix routes a said packet to an outlet of that matrix appropriate to a part of the address information of that packet, so that a packet is progressed through the switching network in a stage-by-stage manner under the control of the processing means of the appropriate ones of said matrices, and in which all packets for the same connection are conveyed over the same route via the switching network.

Claim 6

An automatic telecommunication switching system in which intelligence is handled in packet manner, in which the system includes a plural-stage folded switching network with the terminals served by the system connected to one side of the network, in which each connection between two of said terminals is set up via two half-connections one of which extends into the network from said one side and the other of which comes out of the network to said one side, in which each stage of the switching network includes a number of co-ordinate matrices each including a number of semiconductor cross-points, each such matrix interconnecting a plurality of matrix inlets and matrix outlets, in which each said switching matrix has its own memory means and its own processing means so that control of the system is at least partly distributed, in which when an intelligence packet traversing the network between two of said terminals arrives at a said matrix that packet is routed into that matrix's memory means and its address information is examined by that matrix's processing means to ascertain how the packet is to be routed, in which in response to said examination the processing means at a said matrix routes a said packet to an outlet of that matrix appropriate to a part of the address information of that packet, so that a packet is progressed through the switching network in a stage-by-stage manner under the control of the processing means of the appropriate ones of said matrices, and in which all packets for the same connection are conveyed over the same route via the switching network.

Claim 7

A system as claimed in claim 8, in which for a connection to be set up the number of stages that connection extends into the network is variable, the shortest possible path being used.