Processor

Claim 2

A processor according to claim I, wherein said dual-port RAM is provided therein with a specific information transmission area, said dual-port RAM having a function of raising a hardware interrupt, in response to an access to said area by any one of said CPUs, to said bus accessing CPU or to another CPU.

Claim 3

A processor according to claim I, wherein said common bus switch implements common bus access control in master-slave mode, in which said two CPUs are ranked such that one CPU operates as a main CPU and another CPU operates as a background CPU, said main CPU normally having access right to said common bus, while said background CPU issuing a bus access request signal to said main CPU when need of access to said common bus has arisen, said main CPU, upon recognition of said bus access request signal, entering a halt state at a time point when said background CPU is ready to access to said common bus and, at the same time, issuing an access grant signal to said background CPU to allow said background CPU to make access to said common bus, said halt state of said main CPU being lifted in response to the removal of said bus access request signal upon completion of common bus access by said background CPU, with the common bus access right being returned to said main CPU.

Claim 4

A processor according to claim I or 2, wherein said dual-port RAM is provided in a specific information transmission area thereof with interrupt generating registers on itself and interrupt generating flip-flops (68, 69) for generating an interrupt to each of said two CPUs, an instruction, which is written by one CPU into one of said interrupt generating registers corresponding to a CPU appointed to execute an instruction processing, being decoded on a hardware basis, a corresponding one of said interrupt generating flip-flops being set to activate an interrupt line (32, 33) so that an interrupt to said appointed CPU is generated, said CPU upon receiving said interrupt making reference, in an interrupt service routine, to said interrupt generating register directed thereto where said instruction has been written to read out said instruction, which is decoded on a hardware basis, causing said flip-flop to be reset and said interrupt line to said appointed CPU to be deactivated, then reception of interrupt being completed.

Claim 5

A processor for constructing a single processor system and controlling a machine (114), said processor comprising, within a base processor element (1) constituting said processor, two CPUs (15, t6) with associated local memories (18, I9) for implementing separately an intelligent processing system and a control processing system of said machine, a dual-port RAM (17) accessible from said CPUs, and a common bus switch circuit (22) for connecting any one of said CPUs to a common bus (12) shared by said CPUs.

Claim 6

A processor for constructing a multiprocessor system and controlling a machine (114), said processor comprising, within a base processor element (I) constituting said processor, a first CPU (16) having a local memory (20) and implementing a process for a control processing system of said machine, a second CPU (15) having a local memory (18) and implementing a process for an intelligent processing system of said machine, a dual-port RAM (17) accessible from said CPUs, a common bus switch circuit (22) for connecting any one of said CPUs to a common bus (12) shared by said CPUs, and a common bus connected to an intelligent processing controller and a control processing controller (III) of said machine.

Claim 7

A processor for constructing a multiprocessor system and controlling a machine (114), said processor comprising, within a base processor element (I), a first CPU (16) having a local memory (20) and implementing a process for a control processing system of said machine, a second CPU (15) having a local memory (18) and implementing a process for an intelligent processing system of said machine, a dual-port RAM (17) accessible from said CPUs, and a common bus switch circuit (22) for connecting said CPUs to a common bus, said first CPU being connected to a common bus (14) of said control processing system, while said second CPU being connected to a common bus (100) of said intelligent processing system.