EP0239756A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Process for forming planar chip-level wiring
Assignee: International Business Machines Corp
•
Filing: 1987-02-11
•
Granted: —
•
Expires: 2007-02-11
Abstract
Abstract Disclosed is a process of forming high density, planar, single- or multi-level wiring for an semiconductor integrated circuit chip. On the chip surface (10) is provided a dual layer of an insulator (14) and hardened photoresist (16) having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e.g., metal) layer (22) of a thickness equal to that of the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist (28, 30) is formed filling the metal valleys and obtaining a substantially planar surface (32). The lower component layer (28) is thin and conformal and has a higher etch rate than the upper component layer (30) which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys. Using the plug as etch masks, the exposed metal is removed followed by removal of the remaining hardened photo-resist layer and the plugs leaving a metal pattern coplanar with the insulator layer. This sequence of steps is repeated for multilevel wiring. When only narrow wiring is desired, a single photoresist layer is substituted for the dual photo-resist sacrificial layer.
Inventors
- 👤 Karanam Balasubramanyam
- 👤 Jacob Riseman
- 👤 Anthony John Dally
- 👤 Seiki Ogura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 15:05
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/20; H10P76/202; G; G03; G03F; G03F7/00; G03F7/004; G03F7/09; G03F7/094; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/058; H10W20/062; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/951; Y10S438/963
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
126 words
A process for forming a planar conductive interconnection on a substrate, comprising: providing a substrate covered with a dual layer of an insulator and hardened first photosensitive material, said layer having at least one opening for exposing a substrate region in correspondence therewith; depositing a conductive layer filling said opening to the level of said insulator; forming on the resulting structure a second hardened photosensitive layer having a substantially planar surface despite said opening; anisotropically etching said second photosensitive layer to leave a portion thereof only in said opening in the form of a plug in contact with the conductive layer therein; removing the portion of conductive layer exposed by the etching of said second photosensitive layer; and removing said plug and said first photosensitive layer.
Claim 2
Dependent Claim
126 words
A process for forming a planar conductive interconnection on a substrate, comprising: providing a substrate covered with a dual layer of an insulator and hardened first photosensitive material, said layer having at least one opening for exposing a substrate region in correspondence therewith; depositing a conductive layer filling said opening to the level of said insulator; forming on the resulting structure a second hardened photosensitive layer having a substantially planar surface despite said opening; anisotropically etching said second photosensitive layer to leave a portion thereof only in said opening in the form of a plug in contact with the conductive layer therein; removing the portion of conductive layer exposed by the etching of said second photosensitive layer; and removing said plug and said first photosensitive layer.
Claim 3
Dependent Claim
19 words
The process as in claim 1 wherein said conductive layer has a thickness equal to that of said insulator.
Claim 4
Dependent Claim
13 words
The process as in claim 1 wherein said first photosensitive material is photoresist.
Claim 5
Dependent Claim
13 words
The process as in claim 1 wherein said second photosensitive material is photoresist.
Claim 6
Dependent Claim
18 words
The process as in claim 3 wherein said first photoresist is hardened by thermal baking under vacuum conditions.
Claim 7
Dependent Claim
23 words
The process as recited in claim 3 wherein said first photoresist is hardened by exposure to wavelength in the range of 2000-3000 Å.
Claim 8
Dependent Claim
24 words
The process as recited in claim 4 wherein said second photoresist is hardened by thermal baking at a temperature of 150-220°C in nitrogen ambient.
Claim 9
Dependent Claim
132 words
A process for forming a planar conductive interconnection on a substrate, comprising: providing a substrate covered with a dual layer of an insulator and hardened photosensitive material, said dual layer having wide and narrow openings exposing the substrate in correspondence therewith; depositing a conductive layer filling said openings to the level of said insulator; forming on the resulting structure a sacrificial layer having a substantially planar surface despite said openings, said sacrificial layer being composed of a thin lower photosensitive layer and a thick upper photosensitive layer; anisotropically etching said sacrificial layer to leave portions thereof in the form of plugs in contact with the conductive layer therein; removing the portion of the conductive layer exposed by the etching of said sacrificial layer; and removing said plugs and said hardened photosensitive material.
Claim 10
Dependent Claim
132 words
A process for forming a planar conductive interconnection on a substrate, comprising: providing a substrate covered with a dual layer of an insulator and hardened photosensitive material, said dual layer having wide and narrow openings exposing the substrate in correspondence therewith; depositing a conductive layer filling said openings to the level of said insulator; forming on the resulting structure a sacrificial layer having a substantially planar surface despite said openings, said sacrificial layer being composed of a thin lower photosensitive layer and a thick upper photosensitive layer; anisotropically etching said sacrificial layer to leave portions thereof in the form of plugs in contact with the conductive layer therein; removing the portion of the conductive layer exposed by the etching of said sacrificial layer; and removing said plugs and said hardened photosensitive material.
Claim 11
Dependent Claim
24 words
The process as recited in claim 8 wherein said lower photosensitive layer is selective to said upper photosensitive layer during said anisotropic etching step.
Claim 12
Dependent Claim
16 words
The process as in claim 9 wherein said upper photosensitive layer is composed of photoresist material.
Claim 13
Dependent Claim
16 words
The process as in claim 10 wherein said lower photosensitive layer is composed of photoresist material.
Claim 14
Dependent Claim
31 words
The process as in claim 11 further comprising hardening said upper and lower photoresist layers by subjecting to a baking process at a temperature in the range 150-220°C in nitrogen ambient.
Claim 15
Dependent Claim
13 words
The process as in claim 9 wherein said hardened photosensitive material is photoresist.
Claim 16
Dependent Claim
23 words
The process as in claim 13 wherein said photoresist hardening comprises thermally baking in vacuum at a temperature in the range of 250°-300°C.
Claim 17
Dependent Claim
23 words
The process as in claim 13 wherein said photoresist hardening comprises exposing said photoresist to ultraviolet wavelength in the range of 2000-3000 Å.
Claim 18
Dependent Claim
22 words
The process as in claim 9 wherein said insulator is selected from the group consisting of silicon dioxide, glass and silicon nitride.
Claim 19
Dependent Claim
25 words
The process as recited in claim 9 wherein said conductive material is selected from the group consisting of aluminum, aluminum-copper, aluminum-silicon-copper, molybdenum, tantalum and tungsten.
Claim 20
Dependent Claim
251 words
A process for forming a planar multilayer metallurgical interconnection pattern on a substrate comprising: (a) forming an insulator layer on said substrate; (b) applying a first photoresist layer on said insulator layer; (c) hardening the first photoresist layer by removing the moisture therein; (d) patterning said photoresist to have a pattern of openings in the form of the desired metallurgical pattern; (e) removing the resultant exposed areas of the insulator by reactive ion etching; (f) depositing over said substrate a blanket continuous conductive metal layer, said conductive layer having a mesa and valley configuration conforming to the topography on the surface of said substrate, the thickness of said metal layer being equal to the thickness of said insulator layer; (g) forming on the resultant structure a dual photoresist layer having an essentially planar surface despite said topography on the surface of said substrate by applying a thin lower photoresist layer conforming to the topography of said metal layer followed by a thick upper photoresist layer, said thin lower photo-resist being characterized by selectivity with respect to said thick upper photoresist during etching thereof; (h) reactive ion etching said dual layer to expose said metal mesas while leaving said metal valleys masked by said dual photoresist layer; (i) etching said metal to remove metal above said first photoresist layer; (j) removing said first photoresist and said dual photoresist corresponding to said metal valleys, thereby obtaining planar first level metallurgical pattern; and (k) repeating steps (a) through (j) for planar multilevel metallurgical pattern.
Claim 21
Dependent Claim
251 words
A process for forming a planar multilayer metallurgical interconnection pattern on a substrate comprising: (a) forming an insulator layer on said substrate; (b) applying a first photoresist layer on said insulator layer; (c) hardening the first photoresist layer by removing the moisture therein; (d) patterning said photoresist to have a pattern of openings in the form of the desired metallurgical pattern; (e) removing the resultant exposed areas of the insulator by reactive ion etching; (f) depositing over said substrate a blanket continuous conductive metal layer, said conductive layer having a mesa and valley configuration conforming to the topography on the surface of said substrate, the thickness of said metal layer being equal to the thickness of said insulator layer; (g) forming on the resultant structure a dual photoresist layer having an essentially planar surface despite said topography on the surface of said substrate by applying a thin lower photoresist layer conforming to the topography of said metal layer followed by a thick upper photoresist layer, said thin lower photo-resist being characterized by selectivity with respect to said thick upper photoresist during etching thereof; (h) reactive ion etching said dual layer to expose said metal mesas while leaving said metal valleys masked by said dual photoresist layer; (i) etching said metal to remove metal above said first photoresist layer; (j) removing said first photoresist and said dual photoresist corresponding to said metal valleys, thereby obtaining planar first level metallurgical pattern; and (k) repeating steps (a) through (j) for planar multilevel metallurgical pattern.
Claim 22
Dependent Claim
27 words
The process as recited in claim 18 wherein hardening of said first photoresist is accomplished by heating in vacuum at a temperature in the range of 250-300°C.
Claim 23
Dependent Claim
29 words
The process as recited in claim 19 wherein hardening of said first photoresist is accomplished by subjecting said first photoresist to ultraviolet wavelength in the range of 2000-3000 Å.
Claim 24
Dependent Claim
31 words
The process as recited in claim 19 wherein said conductive metal layer is a sandwich structure composed of a relatively thin lower conductive layer and a relatively thick upper conductive layer.
Claim 25
Dependent Claim
18 words
The process as recited in claim 19 further comprising hardening each of said lower and upper photoresist layers.
Claim 26
Dependent Claim
27 words
The process as in claim 22 wherein said hardening comprises subjecting said lower and upper photoresist layers to a temperature of about 80-200°C for a short period.
Claim 27
Dependent Claim
29 words
The process as recited in claim 21 wherein said thin lower conductive layer is composed of a conductive material selected from the group consisting of titanium, tungsten and titanium-tungsten.
Claim 28
Dependent Claim
27 words
The process as recited in claim 21 wherein said thick upper conductive layer is selected from the group consisting of aluminum, aluminum-silicon, aluminum-silicon-copper, molybdenum, tantalum and tungsten.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.