Overlapped control store

Claim 2

A control store system characterised by: first and second control store copies; means for providing a clock signal for defin­ing clock cycles; means for providing an address at each clock cycle; means, coupled to said first and second con­trol store copies, said address providing means, and said clock signal providing means, for beginning the access of control information from said first and second copies on alternate clock cycles; and feedback means, coupled to said address provid­ing means and to said control store copies, for direct­ing part of said accessed control information to said address providing means.

Claim 3

A control store system as claimed in claim 1 wherein said address providing means comprises: an address storage element; a branch MUX having a control input port and first and second data input ports; and wherein said feedback means comprises: a control bus coupled to said branch MUX control input port; and an address bus coupled to said first branch MUX data input port.

Claim 4

A memory system of the type having first and second memory banks for storing copies of a set of data elements, with each memory bank having a set of CS memory elements for storing a subset of the bits comprising the data elements and having a spare memory element, a system for recovering from soft errors and for dynamically reconfiguring the first memory bank to compensate for a defective CS memory element, characterised by: means for detecting an error in a given data element stored in the first memory bank during a readout of said data set; means for substituting the given data element stored in said second memory bank for the erroneous data element during the data set read out; means for identifying a defective CS memory element in the first memory bank; means for writing the data stored in the sec­ond memory bank, corresponding to the data stored in said defective CS memory element, into the spare memory element of the first memory bank; and means for substituting the output of the spare memory element in the first memory bank for the output of the defective memory element.

Claim 5

A memory system of the type having first and second memory banks for storing copies of a set of data elements, with each memory bank having a set of CS memory elements for storing a subset of the bits comprising the data elements and having a spare memory element, a system for recovering from soft errors and for dynamically reconfiguring the first memory bank to compensate for a defective CS memory element, characterised by: means for detecting an error in a given data element stored in the first memory bank during a readout of said data set; means for substituting the given data element stored in said second memory bank for the erroneous data element during the data set read out; means for identifying a defective CS memory element in the first memory bank; means for writing the data stored in the sec­ond memory bank, corresponding to the data stored in said defective CS memory element, into the spare memory element of the first memory bank; and means for substituting the output of the spare memory element in the first memory bank for the output of the defective memory element.

Claim 6

A memory system of the type having first and second memory banks for storing copies of a set of data elements, and a system for recovering from soft errors which is characterised by: means for detecting an error in a given data element stored in the first memory bank during a read out of said data set; and means for substituting the given data element stored in said second memory bank for the erroneous data element during the read out of the data set read out.

Claim 7

A memory system of the type having first and second memory banks for storing copies of a set of data elements, and a system for recovering from soft errors which is characterised by: means for detecting an error in a given data element stored in the first memory bank during a read out of said data set; and means for substituting the given data element stored in said second memory bank for the erroneous data element during the read out of the data set read out.

Claim 8

A memory system of the type having first and second memory banks for storing copies of a set of data elements, with each memory bank having a set of CS memory elements for storing a subset of the bits comprising the data elements and having a spare memory element, and a system for dynamically reconfiguring the first memory bank to compensate for a defective CS memory element and characterised by:- means for identifying a defective CS memory element in the first memory bank; means for writing the data stored in the sec­ond memory bank, corresponding to the data stored in said defective CS memory element, into the spare memory element of the first memory bank; and means for substituting the output of the spare memory element in the first memory bank for the output of the defective memory element.

Claim 9

A memory system of the type having first and second memory banks for storing copies of a set of data elements, with each memory bank having a set of CS memory elements for storing a subset of the bits comprising the data elements and having a spare memory element, and a system for dynamically reconfiguring the first memory bank to compensate for a defective CS memory element and characterised by:- means for identifying a defective CS memory element in the first memory bank; means for writing the data stored in the sec­ond memory bank, corresponding to the data stored in said defective CS memory element, into the spare memory element of the first memory bank; and means for substituting the output of the spare memory element in the first memory bank for the output of the defective memory element.

Claim 10

An improved interleaved memory system operating at a system clock rate, characterised by: first and second memory banks, each having an ADR port for receiving ADRs, with each memory bank stor­ing a copy of an identical data set with corresponding data elements stored at the same ADR in each memory element; means for generating a series of ADRs at the system clock rate and for directing said ADRs to an ADRGEN output port; first storage means for storing an ADR received at a first ADR input port upon receipt of a first open signal and for directing said stored ADR to a first ADR output port with said first ADR output port coupled to the ADR port of said first memory bank; second storage means for storing an ADR re­ceived at a second ADR input port upon receipt of a second open signal and for directing said stored ADR to a second ADR output port with said second ADR input port coupled to said ADRGEN output port and said second ADR output port coupled to the ADR port of said second memory bank; signal directing means, having first and sec­ond SDM input ports coupled to the ADRGEN output port and first ADR output port, respectively, having an SDM output port coupled to said second ADR input port and having an SDM control signal input port for receiving an SDM control signal, said SDM being arranged to couple said first SDM input port to said SDM output port when said SDM control signal is in a first state and to couple said second SDM input port to said SDM output port when said first SDM control signal is in a second state; sequential signal generating means, having an error indication port, for generating said first and second open signals on alternating clock cycles when no error indication is received; means for detecting an error in a data element read from a given ADR in the first memory bank and for generating an error indication when the error is de­tected at a given clock cycle; and means, adapted to receive said error indica­tion, for delaying the generation of the first open signal for a recovery time interval, being a selected number of clock cycles after the given clock cycle, to store the given ADR in said first ADR storage means during said recovery time interval, for setting the state of said SDM control signal to the second state during the recovery time interval to couple the first ADR output port to the second ADR input port, and for generating a second open signal during the recovery time interval to store the given ADR in said second ADR storage means so that the data element stored at the given ADR in said said memory bank is accessed.

Claim 11

An improved interleaved memory system operating at a system clock rate, characterised by: first and second memory banks, each having an ADR port for receiving ADRs, with each memory bank stor­ing a copy of an identical data set with corresponding data elements stored at the same ADR in each memory element; means for generating a series of ADRs at the system clock rate and for directing said ADRs to an ADRGEN output port; first storage means for storing an ADR received at a first ADR input port upon receipt of a first open signal and for directing said stored ADR to a first ADR output port with said first ADR output port coupled to the ADR port of said first memory bank; second storage means for storing an ADR re­ceived at a second ADR input port upon receipt of a second open signal and for directing said stored ADR to a second ADR output port with said second ADR input port coupled to said ADRGEN output port and said second ADR output port coupled to the ADR port of said second memory bank; signal directing means, having first and sec­ond SDM input ports coupled to the ADRGEN output port and first ADR output port, respectively, having an SDM output port coupled to said second ADR input port and having an SDM control signal input port for receiving an SDM control signal, said SDM being arranged to couple said first SDM input port to said SDM output port when said SDM control signal is in a first state and to couple said second SDM input port to said SDM output port when said first SDM control signal is in a second state; sequential signal generating means, having an error indication port, for generating said first and second open signals on alternating clock cycles when no error indication is received; means for detecting an error in a data element read from a given ADR in the first memory bank and for generating an error indication when the error is de­tected at a given clock cycle; and means, adapted to receive said error indica­tion, for delaying the generation of the first open signal for a recovery time interval, being a selected number of clock cycles after the given clock cycle, to store the given ADR in said first ADR storage means during said recovery time interval, for setting the state of said SDM control signal to the second state during the recovery time interval to couple the first ADR output port to the second ADR input port, and for generating a second open signal during the recovery time interval to store the given ADR in said second ADR storage means so that the data element stored at the given ADR in said said memory bank is accessed.

Claim 12

An improved interleaved memory system operating at a system clock rate characterised by; first and second memory banks, each having first and second ADR ports, respectively, for receiving ADRs, with each memory bank storing a copy of an identi­cal data set with corresponding data elements stored at the same ADR in each memory element; with said first and second memory banks each including a set of CS memory elements having ADR ports coupled to said first ADR output port, with correspond­ing CS memory element in each memory bank for providing selected bits of the data elements stored in said memory bank; a spare memory element in said first memory bank; means for controllably substituting the output of said spare memory element for the output of a selected memory element of said first memory bank; and means for writing the data stored in the memory element of the second memory bank, that corresponds to said selected memory element of said first memory bank, into said spare memory element.

Claim 13

An improved interleaved memory system operating at a system clock rate characterised by; first and second memory banks, each having first and second ADR ports, respectively, for receiving ADRs, with each memory bank storing a copy of an identi­cal data set with corresponding data elements stored at the same ADR in each memory element; with said first and second memory banks each including a set of CS memory elements having ADR ports coupled to said first ADR output port, with correspond­ing CS memory element in each memory bank for providing selected bits of the data elements stored in said memory bank; a spare memory element in said first memory bank; means for controllably substituting the output of said spare memory element for the output of a selected memory element of said first memory bank; and means for writing the data stored in the memory element of the second memory bank, that corresponds to said selected memory element of said first memory bank, into said spare memory element.