Composite QAM-PSK transmission system

Claim 2

A multilevel modulator for modulating a first and a second main data signal and a subdata signal into a composite modulated signal, each of said first and said second main data signals being represented by first through n-th bits where n is a positive integer which is not less than two, said subdata signal being represented by one of a first and a second binary value at a time, wherein the improvement comprises: modulating means responsive to said first and said second main data signals and said subdata signal for modulating said first and said second main data signals and said subdata signal into said composite modulated signal comprising a quadrature amplitude modulated component and a phase modulated component, said quadrature amplitude modulated component being modulated by said first and said second main data signals and having 2 2n output signal points on a phase plane, said phase modulated component being modulated by said subdata signal.

Claim 3

A multilevel modulator as claimed in Claim l, wherein said modulating means comprises: phase modulating means responsive to a pair of quadrature-phase carrier signals and said subdata signal for phase modulating said pair of quadrature-phase carrier signals by said subdata signal into said phase modulated component; and quadrature amplitude modulating means responsive to said first and said second main data signals and said phase modulated component for amplitude modulating said phase modulated component by said first and said second main data signals into said composite modulated signal.

Claim 4

A multilevel modulator as claimed in Claim 2, wherein said phase modulated component has a first phase difference of plus α radian relative to said pair of quadrature-phase carrier signals where α is not greater than π/2 2n when said subdata signal has said first binary value, said phase modulated component having a second phase difference of minus α radian relative to said pair of quadrature-phase carrier signals when said subdata signal has said second binary value.

Claim 5

A multilevel modulator as claimed in Claim l, wherein said modulating means comprises: converting means responsive to said first and said second main data signals and said subdata signals for converting said first and said second main data signals by said subdata signal into a first and a second converted signal; and quadrature amplitude modulating means responsive to a pair of quadrature-phase carrier signals and said first and said second converted signals for amplitude modulating said pair of quadrature-phase carrier signals by said first and said second converted signals into said composite modulated signal.

Claim 6

A multilevel modulator for modulating a main data signal and a subdata signal into a composite modulated signal, said main data signal being represented by first through N-th bits where N is an odd number, said subdata signal being represented by one of a first and a second binary value at a time, wherein the improvement comprises: modulating means responsive to said main data signal and said subdata signal for modulating said main data signal and said subdata signal into said composite modulated signal comprising a quadrature amplitude modulated component and a phase modulated component, said quadrature amplitude modulated component being modulated by said main data signal and having 2 N output signal points on a phase plane, said phase modulated component being modulated by said subdata signal.

Claim 7

A multilevel modulator for modulating a main data signal and a subdata signal into a composite modulated signal, said main data signal being represented by first through N-th bits where N is an odd number, said subdata signal being represented by one of a first and a second binary value at a time, wherein the improvement comprises: modulating means responsive to said main data signal and said subdata signal for modulating said main data signal and said subdata signal into said composite modulated signal comprising a quadrature amplitude modulated component and a phase modulated component, said quadrature amplitude modulated component being modulated by said main data signal and having 2 N output signal points on a phase plane, said phase modulated component being modulated by said subdata signal.

Claim 8

A multilevel demodulator for demodulating a composite modulated signal comprising a multilevel quadrature amplitude modulated component modulated by a first and a second main data signal and a phase modulated component modulated by a subdata signal, each of said first and said second main data signals being represented by first through n-th bits and having a first bit rate f₁ where n represents a positive integer which is not less than two, said subdata signal being represented by one of a first and a second binary value at a time and having a second bit rate f₂ which is not greater than said first bit rate divided by a predetermined natural number m, said phase modulated component having a first phase difference of plus α radian when said subdata signal is represented by said first binary value, where α is not greater than π/2 2n , said phase modulated component having a second phase difference of minus α radian when said subdata signal is represented by said second binary value, said demodulator comprising detecting means for phase detecting said composite modulated signal to produce a first and a second phase detection signal, wherein the improvement comprises: reproducing means coupled to said detecting means for reproducing a reproduced subdata signal and a first and a second reproduced main data signal in response to said first and said second phase detection signals.

Claim 9

A multilevel demodulator for demodulating a composite modulated signal comprising a multilevel quadrature amplitude modulated component modulated by a first and a second main data signal and a phase modulated component modulated by a subdata signal, each of said first and said second main data signals being represented by first through n-th bits and having a first bit rate f₁ where n represents a positive integer which is not less than two, said subdata signal being represented by one of a first and a second binary value at a time and having a second bit rate f₂ which is not greater than said first bit rate divided by a predetermined natural number m, said phase modulated component having a first phase difference of plus α radian when said subdata signal is represented by said first binary value, where α is not greater than π/2 2n , said phase modulated component having a second phase difference of minus α radian when said subdata signal is represented by said second binary value, said demodulator comprising detecting means for phase detecting said composite modulated signal to produce a first and a second phase detection signal, wherein the improvement comprises: reproducing means coupled to said detecting means for reproducing a reproduced subdata signal and a first and a second reproduced main data signal in response to said first and said second phase detection signals.

Claim 10

A multilevel demodulator as claimed in Claim 6, wherein said reproducing means comprises: subdata reproducing means responsive to said first and said second phase detection signals for reproducing said reproduced subdata signal; and main data reproducing means responsive to said first and said second phase detection signal for reproducing said first and said second reproduced main data signals in accordance with said reproduced subdata signal.

Claim 11

A multilevel demodulator as claimed in Claim 7, wherein said subdata reproducing means comprises: analog-to-digital converting means responsive to said first and said second phase detection signals for converting said first and said second phase detection signals to a first and a second digital signal; and subdata producing means responsive to said first and said second digital signals for producing said reproduced subdata signal.

Claim 12

A multilevel demodulator as claimed in Claim 8, wherein said subdata producing means comprises: logic circuit means responsive to said first and said second digital signals for carrying out a logical operation on said first and said second digital signals to produce a first and a second logical output signal; and majority circuit means responsive to said first and said second logical output signals for carrying out a majority decision on 2m-bits which are equal to a sum of m-bits of said first logical output signal and m-bits of said second logical output signal to produce a result signal as said reproduced subdata signal.

Claim 13

l0. A multilevel demodulator as claimed in any one of Claims 7 to 9, wherein said main data reproducing means comprises: processing means coupled to said detecting means for processing said first phase detection signal to a first and a second processed digital signal and said second phase detection signal to a third and a fourth processed digital signal; and selecting means coupled to said processing means for selecting one of said first and said second processed digital signals and one of said third and said fourth processed digital signals in accordance with said predetermined one of the binary values of said reproduced subdata signal.

Claim 14

A multilevel demodulator as claimed in Claim l0, wherein said processing means comprises: phase shifting means responsive to said first and said second phase detection signals for shifting a phase of said first phase detection signal to produce a first and a second phase shifted signal and a phase of said second phase detection signal to produce a third and a fourth phase shifted signal, said first and said second phase shifted signals having a leading and a lagging phase of α radian relative to said first phase detection signal, said third and said fourth phase shifted signals having a leading and a lagging phase of α radian relative to said second phase detection signal; analog-to-digital converting means responsive to said first through said fourth phase shifted signals for converting said first through said fourth phase shifted signals to said first through said fourth processed digital signals.

Claim 15

A multilevel demodulator as claimed in Claim 6, wherein said reproducing means comprises: converting means coupled to said detecting means for converting said first and said second phase detection signals to a first and a second converted digital signal; subdata reproducing means responsive to said first and said second converted digital signals for reproducing said reproduced subdata signal; main data reproducing means responsive to said first and said second converted digital signals for reproducing said first and said second reproduced main data signals in accordance with said reproduced subdata signal.

Claim 16

A multilevel demodulator as claimed in Claim l2, wherein said subdata reproducing means comprises: logic circuit means responsive to said first and said second converted digital signals for carrying out a logical operation on said first and said second converted digital signals to produce a first and a second factor datum; and digital processing means responsive to said first and said second converted digital signals and said first and said second factor data for processing said first and said second converted digital signals and said first and said second factor data into said reproduced subdata signal.

Claim 17

A multilevel demodulator as claimed in Claim l3, wherein said digital processing means comprises: a first multiplier responsive to said first converted digital signal and said first factor datum for multiplying said first converted digital signal by said first factor datum to produce a first multiplication signal; a second multiplier responsive to said second converted digital signal and said second factor datum for multiplying said second converted digital signal by said second factor datum to produce a second multiplication signal; a subtracter responsive to said first and said second multiplication signals for subtracting said first multiplication signal from said second multiplication signal to produce a subtraction result signal; and a majority circuit responsive to said subtraction result signal for carrying out a majority decision on a succession of m bits of said subtraction result signal to produce a discrimination signal as said reproduced subdata signal.

Claim 18

A multilevel demodulator as claimed in Claim l3, wherein said digital processing means comprises: a first multiplier responsive to said first converted digital signal and said first factor datum for multiplying said first converted digital signal by said first factor datum to produce a first multiplication signal; a second multiplier responsive to said second converted digital signal and said second factor datum for multiplying said second converted digital signal by said second factor datum to produce a second multiplication signal; a subtracter responsive to said first and said second multiplication signals for subtracting said first multiplication signal from said second multiplication signal to produce a subtraction result signal; a digital-to-analog converter coupled to said subtracter for converting said subtraction result signal to an analog signal; a low-pass filter coupled to said digital-to-analog converter for extracting a predetermined band of said analog signal to produce a filtered signal; and an analog-to-digital converter coupled to said low-pass filter for converting said filtered signal to a digital signal as said reproduced subdata signal.

Claim 19

A multilevel demodulator as claimed in Claim l2, wherein said main data reproducing means comprises: logic circuit means responsive to said reproduced subdata signal for carrying out a logical operation on said reproduced subdata signal to produce a first and a second factor datum; and digital processing means responsive to said first and said second converted digital signals and said first and said second factor data for processing said first and said second converted digital signals and said first and said second factor data into said first and said second reproduced main data signals.

Claim 20

A multilevel demodulator as claimed in Claim l6, wherein said digital processing means comprises: a first multiplier responsive to said first converted digital signal and said first factor datum for multiplying said first converted digital signal by said first factor datum to produce a first multiplication signal; a second multiplier responsive to said second converted digital signal and said second factor datum for multiplying said second converted digital signal by said second factor datum to produce a second multiplication signal; a first adder responsive to said first converted digital signal and said second multiplication signal for adding said first converted digital signal to said second multiplication signal to produce said first reproduced main data signal; and a second adder responsive to said second converted digital signal and said first multiplication signal for adding said second converted digital signal to said first multiplication signal to produce said second reproduced main data signal.

Claim 21

A multilevel demodulator for demodulating a composite modulated signal comprising a multilevel quadrature amplitude modulated component modulated by a main data signal and a phase modulated component modulated by a subdata signal, said main data signal being represented by first through N-th bits and having a first bit rate f₁ where N represents an odd number, said subdata signal being represented by one of a first and a second binary value at a time and having a second bit rate f₂ which is not greater than said first bit rate divided by a predetermined natural number m, said phase modulated component having a first phase difference of plus α radian when said subdata signal is represented by said first binary value, where α is not greater than π/2 N , said phase modulated component having a second phase difference of minus α radian when said subdata signal is represented by said second binary value, said demodulator comprising detecting means for phase detecting said composite modulated signal to produce a first and a second phase detection signal, wherein the improvement comprises: reproducing means coupled to said detecting means for reproducing a reproduced subdata signal and a first and a second reproduced main data signal in response to said first and said second phase detection signals.

Claim 22

A multilevel demodulator for demodulating a composite modulated signal comprising a multilevel quadrature amplitude modulated component modulated by a main data signal and a phase modulated component modulated by a subdata signal, said main data signal being represented by first through N-th bits and having a first bit rate f₁ where N represents an odd number, said subdata signal being represented by one of a first and a second binary value at a time and having a second bit rate f₂ which is not greater than said first bit rate divided by a predetermined natural number m, said phase modulated component having a first phase difference of plus α radian when said subdata signal is represented by said first binary value, where α is not greater than π/2 N , said phase modulated component having a second phase difference of minus α radian when said subdata signal is represented by said second binary value, said demodulator comprising detecting means for phase detecting said composite modulated signal to produce a first and a second phase detection signal, wherein the improvement comprises: reproducing means coupled to said detecting means for reproducing a reproduced subdata signal and a first and a second reproduced main data signal in response to said first and said second phase detection signals.