Colour graphics control system

Claim 2

A colour graphics control system for generating electrical signal values for respective colour inputs to a raster scan colour display unit in response to a succession of pixel values derived from a pixel memory device storing pixel values for a scanning sequence, said control system comprising: a) memory means in the form of RAM having a plurality of addressable locations each storing a digital colour value, b) digital to analog converter means for receiving digital colour values from said RAM and in response to each different colour value generating a different combination of analog electrical signals representing respectively red, blue and green colour values for each pixel in a raster scan display, c) timing means for indicating a pixel frequency corresponding to that of the raster scan and generating timing control signals for synchronising the generation of said analog signals at said pixel frequency, d) RAM accessing means for receiving a succession of pixel values from said pixel memory device at the pixel frequency and in response to each pixel value effecting a multi-stage accessing operating including addressing a corresponding location of the RAM and reading from the location a digital colour value for supplying to said digital to analog converter means, e) an interface connected to said RAM and arranged for connection to a microprocessor or other controller to permit the microprocessor or other controller to write different digital colour values into one'or more locations in said RAM, f) said timing means being arranged to control each successive stage of RAM accessing wherein a pipeline effect is achieved with a cycle time of more than one pixel period for addressing a RAM location and reading the digital colour value for each pixel value.

Claim 3

A colour graphics control system according to claim 1 wherein said timing means is arranged to control RAM accessing so that each accessing operation extends over two successive pixel periods.

Claim 4

A colour graphics control system according to claim 1 wherein each location of the RAM stores a multi bit data value having bit groups representing red, blue and green colour values, and said digital to analog converter means comprises three digital to analog converters arranged to receive separately a respective bit group so that they operate in parallel to provide simultaneously red, blue and green analog signals.

Claim 5

A colour graphics control system according to claim 1 in which said interface includes temporary store means for receiving data from a microprocessor or other controller for use in writing into said RAM and access means for controlling loading of data into said temporary store means, said access means being operable independently of the pixel frequency to permit asynchronous loading of data into said interface from a microprocessor or other controller.

Claim 6

A colour graphics control system according to claim 4 in which said temporary store means includes means for holding a RAM address and means for holding a digital colour value to be written into said RAM address.

Claim 7

A colour graphics control system according to claim 5 in which means is provided for incrementing the RAM address in said temporary store means after each writing operation.

Claim 8

A colour graphics control system according to claim 4 in which the timing means includes a pixel clock providing signals at the pixel frequency and said interface includes synchronising means arranged to receive timing signals from said timing means whereby a writing operation from the interface into said RAM is synchronised with the pixel clock.

Claim 9

A colour graphics control system according to claim 7 in which the writing operating is a multi-stage operation having a cycle time of more than one pixel period, each stage being controlled by said timing means so that a pipeline effect is achieved in writing in synchronism with the pixel clock over more than one period of the pixel frequency.

Claim 10

A colour graphics control system according to claim 3 wherein each digital to analog converter includes a plurality of parallel current sources connected to a common reference voltage, switch means responsive to said digital colour value to control the number of current sources switched to form an analog output, and means for stabilising the current derived from each current source so that it is independent of the number of parallel current sources that are switched on or off and thereby reduce nonlinearity of the digital to analog conversion.

Claim 11

A colour graphics control system according to claim 9 in which each current source comprises a first transistor with said reference voltage forming a gate voltage for the transistor, the stabilising means comprising differential amplifier circuit means responsive to current fluctuations through said first transistor and arranged to provide a compensating voltage to the gate of a further transistor in series with said first transistor.

Claim 12

A colour graphics control system according to claim 3 in which each digital to analog converter includes a plurality of current sources together with switch means responsive to said digital colour value to control the number of current sources operable in response to a digital colour value, said current sources forming a plurality of groups of different numbers of current sources, all the current sources in each group being arranged to be switched on or off together by a single binary coded signal.

Claim 13

A colour graphics control system according to claim 1 wherein the digital to analog converter means includes means for receiving a multi-bit binary encoded signal representing a digital colour value for conversion to an analog signal, and a plurality of selectively operable current sources with switch means for operating a selected number of current sources corresponding to the value of said multi-bit signal, said current sources being grouped into a plurality of groups wherein all current sources in a group are switched together, the groups having numbers of current sources corresponding to bits of different significance in said multi-bit signal with the largest group having a number of current sources representing less than the bit of maximum significance in said multi-bit signal, decoding means being provided for decoding said multi-bit signal and providing a number of switch actuating signals greater than the number of bits in said multi-bit signal, each switch actuating signal being provided for a respective group of current sources, thereby reducing the magnitude of any group of current sources necessary to be switched at any time.

Claim 14

A colour graphics control system according to claim 12 wherein the groups of current sources include a first group including progressively increasing numbers of current sources each corresponding to the numerical value of successive bit locations in said multi-bit signal and a second group at least one of which includes the maximum number of current sources to be switched as a single group, the second group being combined to represent the bit of maximum significance in the multi-bit signal.

Claim 15

A colour graphics control system according to claim 1 wherein said RAM, interface and digital to analog converter means are formed on a single integrated circuit device.

Claim 16

A colour graphics control system according to claim 14 wherein each addressable location in said RAM is arranged to store an 18-bit word, said word having three groups of six bits representing respectively the colour values for red, blue and green.

Claim 17

A colour graphics control system according to claim 15 wherein said RAM provides 256 addressable word locations.

Claim 18

A colour graphics control system for generating electrical signal values for respective colour inputs to a raster scan colour display unit in response to a succession of pixel values derived from a pixel memory device storing pixel values for a scanning sequence, said control system comprising: a) memory means in the form of RAM having a plurality of addressable locations each storing a digital colour value, b) digital to analog converters for red, blue and green signals respectively each arranged to receive a multi-bit digital colour value from said RAM and in response to each colour value generate a corresponding analog electrical signal for each pixel in a raster scan display, each said digital to analog converter means including means for receiving a multi-bit binary encoded signal and a plurality of selectively operable current sources with switch means for operating a selected number of current sources corresponding to the value of said multi-bit signal, said current sources being grouped into a plurality of groups wherein all current sources in a group are switched together, the groups having numbers of current sources corresponding to bits of different significance in said multi-bit signal with the largest group having a number of current sources representing less than the bit of maximum significance in said multi-bit signal, decoding means being provided for decoding said multi-bit signal and providing a number of switch actuating signals greater than the number of bits in said multi-bit signal, each switch actuating signal being provided for a respective group of current sources, c) timing means for indicating a pixel frequency corresponding to that of the raster scan and generating timing control signals for synchronising the generation of said analog signals at said pixel frequency, d) RAM accessing means for receiving a succession of pixel values from said pixel memory device at the pixel frequency and in response to each pixel value effecting a multi-stage accessing operating including addressing a corresponding location of the RAM and reading from the location a digital colour value for supplying to said digital to analog converter means, and e) an interface connected to said RAM and arranged for connection to a microprocessor or other controller to permit the microprocessor or other controller to write different digital colour values into one or more locations in said RAM, f) said timing means being arranged to control each successive stage of RAM accessing wherein a pipeline effect is achieved with a cycle time of more than one pixel period for addressing a RAM location and reading the digital colour value for each pixel value.

Claim 19

A colour graphics control system for generating electrical signal values for respective colour inputs to a raster scan colour display unit in response to a succession of pixel values derived from a pixel memory device storing pixel values for a scanning sequence, said control system comprising: a) memory means in the form of RAM having a plurality of addressable locations each storing a digital colour value, b) digital to analog converters for red, blue and green signals respectively each arranged to receive a multi-bit digital colour value from said RAM and in response to each colour value generate a corresponding analog electrical signal for each pixel in a raster scan display, each said digital to analog converter means including means for receiving a multi-bit binary encoded signal and a plurality of selectively operable current sources with switch means for operating a selected number of current sources corresponding to the value of said multi-bit signal, said current sources being grouped into a plurality of groups wherein all current sources in a group are switched together, the groups having numbers of current sources corresponding to bits of different significance in said multi-bit signal with the largest group having a number of current sources representing less than the bit of maximum significance in said multi-bit signal, decoding means being provided for decoding said multi-bit signal and providing a number of switch actuating signals greater than the number of bits in said multi-bit signal, each switch actuating signal being provided for a respective group of current sources, c) timing means for indicating a pixel frequency corresponding to that of the raster scan and generating timing control signals for synchronising the generation of said analog signals at said pixel frequency, d) RAM accessing means for receiving a succession of pixel values from said pixel memory device at the pixel frequency and in response to each pixel value effecting a multi-stage accessing operating including addressing a corresponding location of the RAM and reading from the location a digital colour value for supplying to said digital to analog converter means, and e) an interface connected to said RAM and arranged for connection to a microprocessor or other controller to permit the microprocessor or other controller to write different digital colour values into one or more locations in said RAM, f) said timing means being arranged to control each successive stage of RAM accessing wherein a pipeline effect is achieved with a cycle time of more than one pixel period for addressing a RAM location and reading the digital colour value for each pixel value.