§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
EP0237218A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method of simulating additional processors in a SIMD parallel processor array

Assignee: Thinking Machines Corp
•
Filing: 1987-02-23
•
Granted: —
•
Expires: 2007-02-23
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method is described for simulating additional processors in a SIMD computer by dividing the memory associated with each processor into a plurality of sub-memories and then operating on each sub-memory in succession as if it were associated with a separate processor. Thus, a first instruction or set of instructions is applied to all the processors of the array to cause at least some processors to process data stored at a first location or locations in the first sub-memory. Thereafter, the same first instruction or set of instructions is applied to all the processors of the array to cause at least some processors to process data stored at the same first location in a second sub-memory. And so forth for each of the sub-memories. By operating a SIMD computer in this fashion, it is possible in effect to vary the number of processors in the array so as to provide the number of processors required for a problem.

Inventors

  • 👤 Daniel W. Hillis
  • 👤 Brewster Kahle
  • 👤 Clifford Lasser
  • 👤 Karl Sims

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-27 23:50
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8023

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 211 words
1 . In a single-instruction multiple-data ( S IM D ) parallel processor comprising a controller and an array of processors controlled in parallel by said controller, each processor comprising an identical input, an identical output, an identical processing element and an identical memory associated with each processing element, the processing element operating in accordance with instructions provided by said controller on data provided by its input and associated memory to produce data at its output, a method of simulating the presence of additional processors in the array comprising the steps of: a) subdividing the memory elements associated with the processing elements in identical fashion to form a plurality of sub-memories associated with each processing memory, b) providing at least a first instruction or first set of instructions from the controller to the processors to cause the processing elements of at least some processors each to process data stored at a first location in a first sub-memory associated with the processing element, and c) at a subsequent time, providing said first instruction or first set of instructions from the controller to the processors to cause the processing elements of at least some processors each to process data stored at the same first location in a second sub-memory associated with the processor.
Claim 2
Dependent Claim 211 words
1 . In a single-instruction multiple-data ( S IM D ) parallel processor comprising a controller and an array of processors controlled in parallel by said controller, each processor comprising an identical input, an identical output, an identical processing element and an identical memory associated with each processing element, the processing element operating in accordance with instructions provided by said controller on data provided by its input and associated memory to produce data at its output, a method of simulating the presence of additional processors in the array comprising the steps of: a) subdividing the memory elements associated with the processing elements in identical fashion to form a plurality of sub-memories associated with each processing memory, b) providing at least a first instruction or first set of instructions from the controller to the processors to cause the processing elements of at least some processors each to process data stored at a first location in a first sub-memory associated with the processing element, and c) at a subsequent time, providing said first instruction or first set of instructions from the controller to the processors to cause the processing elements of at least some processors each to process data stored at the same first location in a second sub-memory associated with the processor.
Claim 3
Dependent Claim 31 words
The method of claim 1 further comprising the steps of repeating steps (b) and (c) on new data stored at the same first locations in the first and second sub-memories. i
Claim 4
Dependent Claim 28 words
The method of claim 1 further comprising the steps of repeating steps (b) and (c) on data stored at a second location in the first and second sub-memories.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag