Dynamic random access memory having trench capacitor

Claim 2

A dynamic random access memory having a trench capacitor, comprising: a semiconductor substrate; a trench formed in said semiconductor substrate; an insulating layer formed on an inner surface of said trench and having an opening in bottom; a first conductive layer formed at the opening position and on said insulating layer, said first conductive layer being ohmically connected to said semiconductor substrate at said opening; a dielectric layer formed on said first conductive layer; a second conductive layer formed on said dielectric layer so as to fill said trench, said first conductive layer, said dielectric layer, and said second conductive layer constituting a charge storage capacitor; and a MIS transistor formed in said semiconductor substrate, wherein said second conductive layer is ohmically connected to a source or drain region of said MIS transistor.

Claim 3

A memory according to claim 1, wherein said second conductive layer is ohmically connected to the source or drain region through a third conductive layer. or 2

Claim 4

A memory according to claim 1/ wherein said semiconductor substrate is a single semiconductor substrate of one conductivity type. 2 or 3t

Claim 5

A memory according to claim 1, / where.in said semiconductor substrate comprises a semiconductor substrate of one conductivity type having a semiconductor layer of the other conductivity type thereon, said trench reaches said semiconductor layer of one conductivity type, and said first conductive layer is ohmically connected to said semiconductor substrate of one conductivity type through said opening.

Claim 6

A dynamic random access memory having a trench capacitor, comprising: a semiconductor substrate of one conductivity type; a buried layer of the other conductivity type formed in said semiconductor substrate; a semiconductor layer formed on said semiconductor substrate having said buried layer; a trench extending through said semiconductor layer and reaching the buried layer of the other conductivity type; an insulating layer formed on an inner side surface of said trench; a first conductive layer formed on said insulating layer formed on said trench and having a lower portion ohmically connected to said buried layer; a dielectric layer formed on said first conductive layer on the inner surface of said trench; a second conductive layer filled in said trench and formed on said dielectric layer; said first conductive layer, said dielectric layer, and said second conductive layer constituting a charge storage capacitor; and a MIS transistor for switching charging or discharging of said charge storage capacitor, wherein said second conductive layer is ohmically connected to one of source and drain regions of said MIS transistor, and said first conductive layer is supplied, through said buried layer of the other conductivity type, with a bias voltage different from that supplied to said semiconductor substrate.

Claim 7

A dynamic random access memory having a trench capacitor, comprising: a semiconductor substrate of one conductivity type; a buried layer of the other conductivity type formed in said semiconductor substrate; a semiconductor layer formed on said semiconductor substrate having said buried layer; a trench extending through said semiconductor layer and reaching the buried layer of the other conductivity type; an insulating layer formed on an inner side surface of said trench; a first conductive layer formed on said insulating layer formed on said trench and having a lower portion ohmically connected to said buried layer; a dielectric layer formed on said first conductive layer on the inner surface of said trench; a second conductive layer filled in said trench and formed on said dielectric layer; said first conductive layer, said dielectric layer, and said second conductive layer constituting a charge storage capacitor; and a MIS transistor for switching charging or discharging of said charge storage capacitor, wherein said second conductive layer is ohmically connected to one of source and drain regions of said MIS transistor, and said first conductive layer is supplied, through said buried layer of the other conductivity type, with a bias voltage different from that supplied to said semiconductor substrate.

Claim 8

A memory according to claim 5, wherein said second conductive layer is ohmically connected to said one of said source and drain regions of said MIS transistor through a third conductive layer.

Claim 9

A dynamic random access memory having a trench capacitor, comprising: a semiconductor substrate of one conductivity type; a trench formed in said semiconductor substrate; an insulating layer formed on an entire inner side surface of said trench, said insulating layer having a thickness which allows a passage of carriers therethrough by a tunnel phenomenon; a first conductive layer formed on said insulating layer and maintained at the same potential as that of said semiconductor substrate through said insulating layer; a dielectric layer formed on said first conductive layer; a second conductive layer of the other conductivity type filled in said trench and formed on said dielectric layer, said first conductive layer, said dielectric layer, and said second conductive layer constituting a charge storage capacitor; and a MIS transistor formed in said semiconductor substrate, wherein said second conductive layer of said charge storage capacitor is ohmically connected to a source or drain region of said MIS transistor.

Claim 10

A dynamic random access memory having a trench capacitor, comprising: a semiconductor substrate of one conductivity type; a trench formed in said semiconductor substrate; an insulating layer formed on an entire inner side surface of said trench, said insulating layer having a thickness which allows a passage of carriers therethrough by a tunnel phenomenon; a first conductive layer formed on said insulating layer and maintained at the same potential as that of said semiconductor substrate through said insulating layer; a dielectric layer formed on said first conductive layer; a second conductive layer of the other conductivity type filled in said trench and formed on said dielectric layer, said first conductive layer, said dielectric layer, and said second conductive layer constituting a charge storage capacitor; and a MIS transistor formed in said semiconductor substrate, wherein said second conductive layer of said charge storage capacitor is ohmically connected to a source or drain region of said MIS transistor.

Claim 11

A memory according to claim 7, wherein said second conductive layer is ohmically connected to said source or drain region of said MIS transistor through a third conductive layer. '