Selective electroless plating of vias in vlsi devices

Claim 2

A selective electroless plating method of forming microminiature conductive plugs in high-aspect-ratio vias defined in a dielectric layer disposed on one main planar surface of a wafer in which integrated-circuit devices are to be fabricated, said method characterized by the steps of forming an active layer (16,18) at the bottoms of vias to be plated, and immersing said wafer in a plating bath comprising a metallic source that provides ions selected from cobalt and nickel.

Claim 3

A method as in claim 1, wherein said source provides nickel or cobalt ions and said active layer comprises material selected from a metallic sillicide, cobalt, nickel, palladium, platinum, copper and aluminum.

Claim 4

A method as in claim 2, wherein said bath comprises a water-based solution at a temperature of about 90 degrees Celsius including approximately 25 grams per liter of NiS0 4 , 60 grams per liter of (NH 4 ) 2 HC 6 H 5 0 7 , 50 grams per liter of NH 4 Cl and 10 grams per liter of NH 4 H 2 P0 2 , with the pH of the bath adjusted to a value of approximately 9 with NH4GH.

Claim 5

A method as in claim 2, wherein said bath comprises a water-based solution at a temperature of about 80 degrees Celsius including approximately 30 grams per liter of NiS0 4 , 3 grams per liter of NaH 2 PO 2 , 2.5 grams per liter of CH 3 COONa and 10 grams per liter of H 3 B0 3 , with the pH of the bath being adjusted to a value approximately between 4 and 6; or wherein said bath comprises a water-based solution at a temperature of about 90 degrees Celsius including approximately 60 grams per liter of CoS0 4 , 2 grams per liter of NiS0 4 , 42 grams per liter of NH 4 S0 4 , 55 grams per liter of (NH 4 ) 2 HC 6 H 5 0 7 and 8 millileters per liter of HPH 2 0 2 , with the pH of the bath adjusted to a value of approximately 8.5 with NH 4 0H.

Claim 6

A method as in claim 1, wherein said active layer comprises a metallic silicide, and wherein said method comprises the further step of forming a patterned conductive layer overlying and in contact with said plated plugs.

Claim 7

A method as in claim 5, wherein said conductive layer comprises aluminum.

Claim 8

A method as in claim 6, wherein at least some portions of said metallic silicide layers overlie source/drain regions of said device.

Claim 9

A method as in claim 7, wherein at least some portions of said metallic silicide layer overlie doped polysilicon regions of said device.

Claim 10

A method as in claim 2, comprising the further step of forming a patterned conductive layer overlying and in contact with said plated plugs, and wherein at least some portions of said active layer overlie a second-mentioned conductive layer of said device.

Claim 11

A method as in claim 9, wherein said second-mentioned conductive layer comprises aluminum.