EP0235977A2 — Bi-directional databus system for supporting supe…

Claim 1

Independent Claim 173 words

A bi-directional busing system for a computer performing scalar and vector operations in which scalar and vector data objects are transferred between a main memory and pipelined functional units by staging through a buffer unit including scalar registers and vector registers, comprising: a bi-directional memory bus means for transferring up to a predetermined number of vector data elements between the main memory and the buffer unit during a multiphase bus transfer cycle in which a plurality of vector data elements can be transferred in one direction during a first phase of a respective transfer cycle and a plurality of vector data elements can be transferred in the other direction during a second phase of said transfer cycle; and a bi-directional function bus means for transferring scalar and vector data elements between the buffer unit and the functional units during said transfer cycle in which the ratio of the number of data objects transferred to the functional units to the number of data objects transferred to the buffer unit corresponds to a predetermined value.

Claim 2

Dependent Claim 173 words

A bi-directional busing system for a computer performing scalar and vector operations in which scalar and vector data objects are transferred between a main memory and pipelined functional units by staging through a buffer unit including scalar registers and vector registers, comprising: a bi-directional memory bus means for transferring up to a predetermined number of vector data elements between the main memory and the buffer unit during a multiphase bus transfer cycle in which a plurality of vector data elements can be transferred in one direction during a first phase of a respective transfer cycle and a plurality of vector data elements can be transferred in the other direction during a second phase of said transfer cycle; and a bi-directional function bus means for transferring scalar and vector data elements between the buffer unit and the functional units during said transfer cycle in which the ratio of the number of data objects transferred to the functional units to the number of data objects transferred to the buffer unit corresponds to a predetermined value.

Claim 3

Dependent Claim 285 words

A bi-directional busing system for supporting the superposition of scalar and vector operations in a computer in which scalar and vector data objects are staged between a main memory of the computer and pipelined functional units of the computer through a buffer, comprising: a bi-directional memory bus means, responsive to memory bus transfer signals, for transferring vector and scalar data elements between the main memory and the buffer during a multiphase bus transfer cycle, in which a plurality of vector data elements can be transferred to the buffer during a first phase of said bus transfer cycle and a plurality of vector data elements can be transferred to the memory during a second phase of said bus transfer cycle; a bi-directional function bus means, responsive to function bus transfer signals, for transferring scalar and vector operand data elements from the buffer to the functional units while concurrently transferring scalar and vector result data from the functional units to the buffer during said bus transfer cycle, in which said operand data is transferred to the functional units during said first transfer cycle phase and said result data is transferred to the buffer during said second transfer cycle; vector and scalar registers in said buffer for staging scalar and vector data elements between said memory bus means and said function bus means in response to data routing signals; and machine control means responsive to a succession of program instructions for providing said memory bus transfer signals and first data routing signals synchronously with said bus transfer cycle in response to memory reference instructions and for providing function bus transfer signals and second data routing signals synchronously with said bus transfer cycle in response to functional operation instructions.

Claim 4

Dependent Claim 285 words

A bi-directional busing system for supporting the superposition of scalar and vector operations in a computer in which scalar and vector data objects are staged between a main memory of the computer and pipelined functional units of the computer through a buffer, comprising: a bi-directional memory bus means, responsive to memory bus transfer signals, for transferring vector and scalar data elements between the main memory and the buffer during a multiphase bus transfer cycle, in which a plurality of vector data elements can be transferred to the buffer during a first phase of said bus transfer cycle and a plurality of vector data elements can be transferred to the memory during a second phase of said bus transfer cycle; a bi-directional function bus means, responsive to function bus transfer signals, for transferring scalar and vector operand data elements from the buffer to the functional units while concurrently transferring scalar and vector result data from the functional units to the buffer during said bus transfer cycle, in which said operand data is transferred to the functional units during said first transfer cycle phase and said result data is transferred to the buffer during said second transfer cycle; vector and scalar registers in said buffer for staging scalar and vector data elements between said memory bus means and said function bus means in response to data routing signals; and machine control means responsive to a succession of program instructions for providing said memory bus transfer signals and first data routing signals synchronously with said bus transfer cycle in response to memory reference instructions and for providing function bus transfer signals and second data routing signals synchronously with said bus transfer cycle in response to functional operation instructions.

Claim 5

Dependent Claim 51 words

The busing system of Claim 2 wherein said memory bus means includes a bi-directional scalar memory bus on which a scalar data element is transferred to said main memory during said first transfer cycle phase and a scalar data element is transferred to said buffer during said second transfer cycle phase.

Claim 6

Dependent Claim 57 words

The busing system of Claim 2 wherein said memory bus means includes one or more bi-directional vector databuses on each of which a vector data element can be transferred to said main memory only during said first transfer cycle phase and a vector data element can be transferred to said buffer only during said second cycle phase.

Claim 7

Dependent Claim 33 words

The busing system of Claim 2 wherein said function bus includes a pair of signal transfer paths and a first of said paths is bi-directional, while the other of said paths is unidirectional.

Claim 8

Dependent Claim 62 words

The busing system of Claim 5 wherein said bi- directional signal path transfers an operand data element to said functional units during said first transfer cycle phase and transfers a result data element to said buffer during said second transfer cycle phase and said unidirectional signal path transfers an operand data element to said functional units during said first transfer cycle phase.

Claim 9

Dependent Claim 34 words

The busing system of Claim 2 wherein the data element transfer capacity of said memory bus means has a predetermined parametric relationship with the operand data element transfer capacity of said function bus means.

Claim 10

Dependent Claim 61 words

The busing system of Claim 2 wherein said control means includes vector control means for staging a stream of operand data elements from said vector registers to said function bus means while staging, in synchronism with said operand stream, a stream of result data elements produced in response to said operand stream from said function bus means to said vector registers.

Claim 11

Dependent Claim 36 words

The busing system of Claim 8 wherein said operand data element stream is interruptable and said vector control means includes scheduling means for interruptably staging said result stream in synchronism with interruptions in said operand stream.

Claim 12

Independent Claim 229 words

A method of transferring scalar and vector data objects in a computer performing scalar and vector processing and having a main memory, a buffer with scalar and vector registers, a plurality of pipelined functional units, one or more bi-directional memory databuses for connecting the main memory to the buffer, and one or more bi-directional function databuses for connecting the buffer to the functional units, comprising: the first step of transferring one or more data elements from said main memory to said buffer registers on a memory databus during result phases of a plurality of successive multiphase bus transfer cycles while transferring one or more data elements from said buffer registers to said main memory during data phases of one or more of said plurality of bus transfer cycles; and the compound step of transferring a string of operand data element pairs from a respective pair of said buffer registers to a functional unit on a function databus, each pair of operand elements being transferred during the data phase of a cycle included in a succession of bus transfer cycles; and returning, in response to said operand string, a string of result data elements from said functional unit to a respective buffer vector register on said function databus, each result data element being transferred during the result phase of a cycle included in said succession of bus transfer cycles. -

Claim 13

Independent Claim 229 words

A method of transferring scalar and vector data objects in a computer performing scalar and vector processing and having a main memory, a buffer with scalar and vector registers, a plurality of pipelined functional units, one or more bi-directional memory databuses for connecting the main memory to the buffer, and one or more bi-directional function databuses for connecting the buffer to the functional units, comprising: the first step of transferring one or more data elements from said main memory to said buffer registers on a memory databus during result phases of a plurality of successive multiphase bus transfer cycles while transferring one or more data elements from said buffer registers to said main memory during data phases of one or more of said plurality of bus transfer cycles; and the compound step of transferring a string of operand data element pairs from a respective pair of said buffer registers to a functional unit on a function databus, each pair of operand elements being transferred during the data phase of a cycle included in a succession of bus transfer cycles; and returning, in response to said operand string, a string of result data elements from said functional unit to a respective buffer vector register on said function databus, each result data element being transferred during the result phase of a cycle included in said succession of bus transfer cycles. -

Claim 14

Dependent Claim 55 words

The method of Claim 10 wherein said memory databus includes two or more databuses and further including, before the first step of transferring, associating a respective one of said memory databuses with a respective one of said buffer registers, and said first step of transferring is performed using said associated memory databus and buffer register.

Claim 15

Dependent Claim 74 words

The method of Claim 10 wherein said function databus includes two or more operand databuses, each for transferring operand data element pairs from said buffer to said functional units, and further including, before the compound step, associating a respective one of said operand databuses with a respective pair of buffer vector registers, said one operand bus being used to transfer said string of operand data element pairs from said associated pair of vector registers.

Claim 16

Dependent Claim 85 words

The method of Claim 12 wherein each said function operand bus includes a pair of signal paths and a respective one of said signal paths is bi-directional and is for transferring result data elements to said buffer, and further including, before the compound step, the step of associating a respective one of said bi-directional signal paths with said one operand databus and with another vector register, said one bi-directional bus being used to return said string of result data elements to said other vector register.

Claim 17

Dependent Claim 42 words

The method of Claim 13 wherein said string of operand data element pairs are interruptable and said compound step includes interrupting the return of said string of result data elements in synchronism with interruptions in said string of operand data element pairs.

Bi-directional databus system for supporting superposition of vector and scalar operations in a computer

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