EP0234598A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Interface circuit for subsystem controller
Assignee: Unisys Corp
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Filing: 1982-11-30
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Granted: —
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Expires: 2002-11-30
Abstract
Abstract An Interface Circuit Card for interfacing a subsystem-controller (called a Network Support Processor) in a data communications system to a main host computer and to a plurality of line support processors which service data communications lines to remote terminals. The Interface Circuit Card provides a data link interface logic circuit (DLI) for connecting the master processor of the Network Support Processor to a distribution control card which contacts the main host system computer. The Interface Circuit Card also provides a message level interface (MLI) logic circuit which connects the master processor to another distribution control card for connection to a line support processor and also to buses which connect to a master memory control card for accessing a shared memory means.
Inventors
- 👤 Craig Weaver Harris
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 18:45
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
427 words
A network support processor (80) which operates as a peripheral controller for data transfers between a host computer (100) and a line communications processor (300) connecting data communication lines to remote terminals, and wherein said network support processor includes first and second processor-controller means (50a,50b), each connected to a shared memory means (90) and said first processor-controller means manages an interface circuit (105i) connecting a main host computer (100) and line communications processor (300) to said network support processor (80), characterised by an interrupt system comprising: a first processor-controller means for controlling data transfers to/from said shared memory means to/from said main host computer and said line communications processor, said first processor-controller means including: a first processor means operating to provide instructions to said interface means and a first memory controller; said first memory-controller for placing data in and accessing data from said shared memory means; a second processor-controller means initiated by said first processor means, said second processor-controller means including: a second processor means for editing and protocol-management of data placed in said shared memory means during transfer to/from said line communications processor and said host computer, said second processor means further providing instructions to a second memory-controller; said second memory-controller for accessing data from said shared memory means to be processed by said second processor means, and for placing processed data back into said shared memory means; an interface circuit, initiated by said first processor means, and providing synchronous communication to said host computer and asynchronous communication to said line communications processor, said interface circuit including: a PROM sequencer for generating data transfer instructions for data transfer between said host computer or said line communications processor to/from said shared memory means, said sequencer including: an interrupt request line to said first processor means for signalling an interrupt when a data transfer sequence is completed by said PROM sequencer; a status register means for holding data indicating what service response is required from said first processor means, said status register means data being fetched by said first processor means to initiate a branch operation to the appropriate service routine; shared memory means connected to said first and second memory-controller, said memory means operating to store data being transferred until such data can be processed by said second processor means; and wherein said first processor means includes: means, responsive to an interrupt signal on said interrupt request line, for switching said first processor means from a normal operating mode to an interrupt mode; means to temporarily store normal mode operating information while executing said interrupt service request.
Claim 2
Dependent Claim
427 words
A network support processor (80) which operates as a peripheral controller for data transfers between a host computer (100) and a line communications processor (300) connecting data communication lines to remote terminals, and wherein said network support processor includes first and second processor-controller means (50a,50b), each connected to a shared memory means (90) and said first processor-controller means manages an interface circuit (105i) connecting a main host computer (100) and line communications processor (300) to said network support processor (80), characterised by an interrupt system comprising: a first processor-controller means for controlling data transfers to/from said shared memory means to/from said main host computer and said line communications processor, said first processor-controller means including: a first processor means operating to provide instructions to said interface means and a first memory controller; said first memory-controller for placing data in and accessing data from said shared memory means; a second processor-controller means initiated by said first processor means, said second processor-controller means including: a second processor means for editing and protocol-management of data placed in said shared memory means during transfer to/from said line communications processor and said host computer, said second processor means further providing instructions to a second memory-controller; said second memory-controller for accessing data from said shared memory means to be processed by said second processor means, and for placing processed data back into said shared memory means; an interface circuit, initiated by said first processor means, and providing synchronous communication to said host computer and asynchronous communication to said line communications processor, said interface circuit including: a PROM sequencer for generating data transfer instructions for data transfer between said host computer or said line communications processor to/from said shared memory means, said sequencer including: an interrupt request line to said first processor means for signalling an interrupt when a data transfer sequence is completed by said PROM sequencer; a status register means for holding data indicating what service response is required from said first processor means, said status register means data being fetched by said first processor means to initiate a branch operation to the appropriate service routine; shared memory means connected to said first and second memory-controller, said memory means operating to store data being transferred until such data can be processed by said second processor means; and wherein said first processor means includes: means, responsive to an interrupt signal on said interrupt request line, for switching said first processor means from a normal operating mode to an interrupt mode; means to temporarily store normal mode operating information while executing said interrupt service request.
Claim 3
Dependent Claim
162 words
A processor according to Claim 8, wherein said first processor-controller means includes: an internal program memory for storing instruction words and data; an external memory means in said first memory-controller for additional storage of data and instructions for controlling said shared memory means; memory address logic means for selecting an address source from a program counter or a memory reference register and including: a program counter for providing addresses to said internal program memory; a memory reference register for providing addresses to said external memory means; an I/O bus from an instruction-execution logic means for carrying instructions to select said program counter or said memory reference register as a source of address data; means to temporarily store the value of said program counter during interrupt operations; means to temporarily store data from said memory reference register during interrupt operations; instruction-execution logic means for receiving instructions from said internal memory or said external memory means; data manipulation logic means for processing data and
Claim 4
Dependent Claim
44 words
EPA 87 103338.7 - Unis y s Corporation I have noticed that owing to a clerical error the dependencies of the Claims filed in the above Divisional Application were incorrect. Accordingly I enclose three copies of new pages of Claims with the dependencies corrected.
Claim 5
Dependent Claim
150 words
processor to/from said shared memory means, said sequencer including: an interrupt request line to said first processor means for signalling an interrupt when a data transfer sequence is completed by said PROM sequencer; a status register means for holding data indicating what service response is required from said first processor means, said status register means data being fetched by said first processor means to initiate a branch operation to the appropriate service routine; shared memory means connected to said first and second memory-controller, said memory means operating to store data being transferred until such data can be processed by said second processor means; and wherein said first processor means includes: means, responsive to an interrupt signal on said interrupt request line, for switching said first processor means from a normal operating mode to an interrupt mode; means to temporarily store normal mode operating information while executing said interrupt service request.
Claim 6
Dependent Claim
150 words
processor to/from said shared memory means, said sequencer including: an interrupt request line to said first processor means for signalling an interrupt when a data transfer sequence is completed by said PROM sequencer; a status register means for holding data indicating what service response is required from said first processor means, said status register means data being fetched by said first processor means to initiate a branch operation to the appropriate service routine; shared memory means connected to said first and second memory-controller, said memory means operating to store data being transferred until such data can be processed by said second processor means; and wherein said first processor means includes: means, responsive to an interrupt signal on said interrupt request line, for switching said first processor means from a normal operating mode to an interrupt mode; means to temporarily store normal mode operating information while executing said interrupt service request.
Claim 7
Dependent Claim
172 words
A processor according to Claim 1, wherein said first processor-controller means includes: an internal program memory for storing instruction words and data; an external memory means in said first memory-controller for additional storage of data and instructions for controlling said shared memory means; memory address logic means for selecting an address source from a program counter or a memory reference register and including: a program counter for providing addresses to said internal program memory; a memory reference register for providing addresses to said external memory means; an I/O bus from an instruction-execution logic means for carrying instructions to select said program counter or said memory reference register as a source of address data; means to temporarily store the value of said program counter during interrupt operations; means to temporarily store data from said memory reference register during interrupt operations; instruction-execution logic means for receiving instructions from said internal memory or said external memory means; data manipulation logic means for processing data and instructions from said internal memory and/or sad external menrory means.
Claim 8
Dependent Claim
52 words
3 . A processor according to Claim 1 or Claim 2, wherein said interface circuit means includes: a sequencer for generating an interrupt signal upon completion of transmission of data to said host computer or completion of received data from said host computer, said interrupt signal being conveyed to said processor means.
Claim 9
Dependent Claim
30 words
A processor according to Claim 3, wherein said interface circuit means further includes: address means, upon initiation of said interrupt mode, to cause a branch to an interrupt service routine.
Claim 10
Dependent Claim
34 words
A processor according to Claim 4, wherein said interface circuit means further includes: a status register for providing added instructions for handling an interrupt request; instruction means to fetch instructions from said status register.
Claim 11
Dependent Claim
58 words
A processor according to Claim 2, wherein said data manipulation logic means includes: an Arithmetic Logic Unit for performing arithmetic and logical operations on data received from an operand register and an accumulator register means; an operand register for temporarily holding data received from said internal memory; an accumulator register means for receiving data from said I/O bus.
Claim 12
Dependent Claim
70 words
A processor according to Claim 6, wherein said accumulator register means includes: a first set of accumulator registers for holding data received on said I/O bus during normal operations; a second set of accumulator registers for holding data received on said I/O bus during interrupt operations; and wherein said first set of registers stores and holds normal mode data, during interrupt operations, for later use on return to normal operations.
Claim 13
Dependent Claim
35 words
A processor according to Claim 7, wherein said instruction-execution logic means includes: an instruction decoder-controller for receiving instruction words and executing instructions; a mode flip-flop.-connected to said decoder-controller and settable to normal or interupt mode.
Claim 14
Dependent Claim
51 words
; 9. A processor according to Claim 2, wirerein said means to temporarily store normal mode operating information includes: a save-register for holding the pre-interrupt data from said memory reference register during interrupt mode operations; a stack memory to hold pre-interrupt value data of the said program counter during interrupt operations.
Claim 15
Dependent Claim
41 words
A processor according to Claim 8, wherein said instruction-execution logic means further includes: a normal operations flag register activated by a first condition of said mode flip-flop; an interrupt operations flag register activated by a second condition of said mode flip-flop.
Claim 16
Dependent Claim
31 words
A processor according to Claim 8, wherein said mode flip-flop includes: means to enable said second set of accumulator registers and disable said first set of accumulator registers during interrupt mode.
Claim 17
Dependent Claim
50 words
A processor according to Claim 8, wherein, upon completion of an interrupt service routine, a return instruction is executed by said first processor means which resets said mode flip-flop to normal mode, and activates said first set of accumulator register means while de-activating said second set of accumulator register means.
References Cited (Backward Citations)
EP0074300A2
Cited
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