Insulated gate field effect transistor and method of manufacture thereof

Claim 1

A method of producing an insulated gate field effect transistor on a first predetermined area of a substrate (1) of semiconductor material having a first type of conductivity, comprising the steps of: forming a first insulating layer (2) on at least a second predetermined area of the substrate (1) completely enclosing the first predetermined area; forming on first region of the first predetermined area a second insulating layer (10; forming above the second insulating layer a conducting layer (9); forming above the conducting layer a third insulating layer (8), the second insulating layer (10) and the conducting layer (9) being arranged to form a gate dielectric and a gate electrode of the transistor, respectively; and forming insulating walls at least on the exposed portions of the edges of the conducting layer so that regions are formed in the first predetermined area which are not covered by any layer and which are separated, characterised by comprising the steps of: forming a layer of semiconductor material (14) at least in the area of the first predetermined area and the second predetermined area; forming on the semiconductor material a layer (15) of material for reducing the differences in depth of the underlying layer; non-selectively etching both the layer (15) of material for reducing the depth differences of the underlying layer and the layer (14) of semiconductor material until at least part of the first insulating layer (2) and the third insulating layer (8) are exposed so as to define portions (16 and 17) of semiconductor material layer (14) which are separate for forming source and drain regions of the transistor; and implanting impurities for forming a second type of conductivity opposite to the first in the portions (16) and (17) of the layer (14) of semiconductor material.

Claim 2

A method of producing an insulated gate field effect transistor on a first predetermined area of a substrate (1) of semiconductor material having a first type of conductivity, comprising the steps of: forming a first insulating layer (2) on at least a second predetermined area of the substrate (1) completely enclosing the first predetermined area; forming on first region of the first predetermined area a second insulating layer (10; forming above the second insulating layer a conducting layer (9); forming above the conducting layer a third insulating layer (8), the second insulating layer (10) and the conducting layer (9) being arranged to form a gate dielectric and a gate electrode of the transistor, respectively; and forming insulating walls at least on the exposed portions of the edges of the conducting layer so that regions are formed in the first predetermined area which are not covered by any layer and which are separated, characterised by comprising the steps of: forming a layer of semiconductor material (14) at least in the area of the first predetermined area and the second predetermined area; forming on the semiconductor material a layer (15) of material for reducing the differences in depth of the underlying layer; non-selectively etching both the layer (15) of material for reducing the depth differences of the underlying layer and the layer (14) of semiconductor material until at least part of the first insulating layer (2) and the third insulating layer (8) are exposed so as to define portions (16 and 17) of semiconductor material layer (14) which are separate for forming source and drain regions of the transistor; and implanting impurities for forming a second type of conductivity opposite to the first in the portions (16) and (17) of the layer (14) of semiconductor material.

Claim 3

A method of producing an insulated gate field effect transistor on a first predetermined area of a substrate (1) of semiconductor material having a first type of conductivity, comprising the steps of: forming a first insulating layer (2) on at least a second predetermined area of the substrate (1) completely enclosing the first predetermined area; forming on a first region of the first predetermined area a second insulating layer (10); forming above the second insulating layer a first conducting layer (9); forming above the first conducting layer a third insulating layer (8), the second insulating layer (10) and the first conducting layer (9) being arranged to form a gate dielectric and a gate electrode of the transistor, respectively; and forming insulating walls at least on the exposed portions of the edges of the conducting layer so that regions are formed in the first predetermined area which are not covered by any layer and which are separated, characterised by comprising the steps of: forming a second conducting layer (14) at least in the area of the first predetermined area and the second predetermined area; forming on the second conducting layer a layer (15) of material for reducing the differences in depth of the underlying layer; and non-selectively etching both th layer (15) of material for reducing the depth differences of the underlying layer and the second conducting layer (14) until at least part of the first insulating layer (2) and the third insulating layer (8) are exposed so as to define transistor source and drain regions (16 and 17) in the remaining portion of the second conducting layer (14).

Claim 4

A method of producing an insulated gate field effect transistor on a first predetermined area of a substrate (1) of semiconductor material having a first type of conductivity, comprising the steps of: forming a first insulating layer (2) on at least a second predetermined area of the substrate (1) completely enclosing the first predetermined area; forming on a first region of the first predetermined area a second insulating layer (10); forming above the second insulating layer a first conducting layer (9); forming above the first conducting layer a third insulating layer (8), the second insulating layer (10) and the first conducting layer (9) being arranged to form a gate dielectric and a gate electrode of the transistor, respectively; and forming insulating walls at least on the exposed portions of the edges of the conducting layer so that regions are formed in the first predetermined area which are not covered by any layer and which are separated, characterised by comprising the steps of: forming a second conducting layer (14) at least in the area of the first predetermined area and the second predetermined area; forming on the second conducting layer a layer (15) of material for reducing the differences in depth of the underlying layer; and non-selectively etching both th layer (15) of material for reducing the depth differences of the underlying layer and the second conducting layer (14) until at least part of the first insulating layer (2) and the third insulating layer (8) are exposed so as to define transistor source and drain regions (16 and 17) in the remaining portion of the second conducting layer (14).

Claim 10

A method of making an insulated gate field effect transistor, comprising forming an insulated gate on a substrate of semiconductor material of a first type of conductivity, characterised in that source and drain regions (16,17) of polycrystalline semiconductor material of a second type of conductivity opposite the first are formed on the substrate (1).

Claim 11

A method of making an insulated gate field effect transistor, comprising forming an insulated gate on a substrate of semiconductor material of a first type of conductivity, characterised in that source and drain regions (16,17) of polycrystalline semiconductor material of a second type of conductivity opposite the first are formed on the substrate (1).