Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
140 words
A field effect transistor comprising: a semi-insulating semiconductor substrate (1), a first semiconductor layer (2), formed on said substrate (1) and serving as a channel region, two second semiconductor layers (3, 3), formed on source and drain regions of said first semiconductor layer (2), and made of a material different from that of said first semiconductor layer (2), two third semiconductor layers (4 1 , 42), formed on said second semiconductor layers (3, 3), made of a material different from that of said second semiconductor layers (3, 3), and doped with a high concentration impurity, source and drain electrodes (6 1 , 62), respectively formed on said third semiconductor layers (4 1 , 42), and a gate electrode (9), formed on a region on said first semiconductor layer (2) between said two third semiconductor layers (4 ,, 42 ) .
Claim 2
Dependent Claim
140 words
A field effect transistor comprising: a semi-insulating semiconductor substrate (1), a first semiconductor layer (2), formed on said substrate (1) and serving as a channel region, two second semiconductor layers (3, 3), formed on source and drain regions of said first semiconductor layer (2), and made of a material different from that of said first semiconductor layer (2), two third semiconductor layers (4 1 , 42), formed on said second semiconductor layers (3, 3), made of a material different from that of said second semiconductor layers (3, 3), and doped with a high concentration impurity, source and drain electrodes (6 1 , 62), respectively formed on said third semiconductor layers (4 1 , 42), and a gate electrode (9), formed on a region on said first semiconductor layer (2) between said two third semiconductor layers (4 ,, 42 ) .
Claim 3
Dependent Claim
53 words
A transistor according to claim 1, characterized in that said semi-insulating semiconductor substrate (1) is an InP substrate, said first semiconductor layer (2) is an n-type InP layer, said second semiconductor layers (3, 3) are GaInAsP layers or GaInAs layers, and said third semiconductor layers (4,, 4 2 ) are n-type InP layers.
Claim 4
Dependent Claim
27 words
A transistor according to claim 1, characterized in that said gate electrode (9) directly contacts said first semiconductor layer (2), and a Schottky barrier is formed therebetween.
Claim 5
Dependent Claim
239 words
An opto-electronic integrated circuit device in which a light-emitting device and a field effect transistor are integrated, characterized in that said light-emitting device is obtained by sequentially stacking a first clad layer (14 1 ), an active layer (151), and a second clad layer (17) on a semi-insulating semiconductor substrate (11), said field effect transistor comprises a channel layer (12) formed on said substrate (11), source and drain layers (14 2 , 14 3 ) with a high impurity concentration formed on said channel layer (12), an etching mask layer (15 2 , 15 3 ) formed on said source and drain layers ( 142 , 143 ), source and drain electro J es (21 1 , 21 2 ) formed directly or through said etching mask layer (15 2 , 15 3 ) on said source and drain layers (14 2 , 14 3 ), and a gate electrode (22) formed on a region of said channel layer (12) between said source and drain layers (14 2 , 14 3 ), said first clad layer (14 1 ) of said light-emitting device and said source and drain layers (142, 14 3 ) of said field effect transistor are formed of the same semiconductor layer, and said active layer (15 1 ) of said light-emitting device and said etching mask layer (15 2 , 15 3 ) of said field effect transistor are formed of the same semiconductor layer.
Claim 6
Dependent Claim
239 words
An opto-electronic integrated circuit device in which a light-emitting device and a field effect transistor are integrated, characterized in that said light-emitting device is obtained by sequentially stacking a first clad layer (14 1 ), an active layer (151), and a second clad layer (17) on a semi-insulating semiconductor substrate (11), said field effect transistor comprises a channel layer (12) formed on said substrate (11), source and drain layers (14 2 , 14 3 ) with a high impurity concentration formed on said channel layer (12), an etching mask layer (15 2 , 15 3 ) formed on said source and drain layers ( 142 , 143 ), source and drain electro J es (21 1 , 21 2 ) formed directly or through said etching mask layer (15 2 , 15 3 ) on said source and drain layers (14 2 , 14 3 ), and a gate electrode (22) formed on a region of said channel layer (12) between said source and drain layers (14 2 , 14 3 ), said first clad layer (14 1 ) of said light-emitting device and said source and drain layers (142, 14 3 ) of said field effect transistor are formed of the same semiconductor layer, and said active layer (15 1 ) of said light-emitting device and said etching mask layer (15 2 , 15 3 ) of said field effect transistor are formed of the same semiconductor layer.
Claim 7
Dependent Claim
137 words
A device according to claim 4, characterized in that said semi-insulating semiconductor substrate (11) is an InP substrate, said channel layer (12) of said field effect transistor is an n-type InP layer formed on the entire surface of said substrate (11), said source and drain layers (14 2 , 14 3 ) with a high impurity concentration of said field effect transistor and said first clad layer (14 1 ) of said light-emitting device are n-type InP layers formed on said channel layer (12), said etching mask layer (15 2 , 15 3 ) of said field effect transistor and said active layer (15 1 ) of said light-emitting device are GaInAsP layers or GaInAs layers formed on saia n-type InP layer, and said second clad layer (17) of said light-emitting device is a p-type InP layer.
Claim 8
Dependent Claim
37 words
A device according to claim 4, characterized in that said field effect transistor is a Schottky gate field effect transistor in which a Schottky barrier is formed between said gate electrode (22) and said channel layer (12).
Claim 9
Dependent Claim
23 words
7 . A device according to claim 4, characterized in that said light-emitting device is a laser diode having a double heterojunction structure.
Claim 10
Independent Claim
381 words
A method of manufacturing an opto-electronic integrated circuit device in which a light-emitting device and a field effect transistor are integrated on a substrate, comprising the steps of growing a first semiconductor layer (12), serving as a channel layer of a field effect transistor, on a semi-insulating semiconductor substrate (11), growing a second semiconductor layer (13), serving as an etching stopper layer and made of a material different from that of said first semiconductor layer (12) on said first semiconductor layer (12), growing a third semiconductor layer (14), serving as a first clad layer (14 1 ) of said light-emitting device and source and drain layers (14 2 , 14 3 ) with a high impurity concentration of said field effect transistor and made of a material different from that of said second semiconductor layer (13), on said second semiconductor layer (13), growing a fourth semiconductor layer (15) serving as an active layer (15 1 ) of said light-emitting device , and an etching mask (15 2 , 15 3 ) used when a gate region of said field effect transistor is recess-etched and made of a material different from that of said third semiconductor layer (14), selectively etching a region around said active layer (15 1 ) of said light-emitting device and said gate region of said field effect transistor of said fourth semiconductor layer (15), sequentially growing a fifth semiconductor layer (17) serving as a second clad layer of said light-emitting device and a sixth semiconductor layer (18) serving as a cap layer, selectively etching a region of said sixth and fifth semiconductor layers (18, 17) characterized in that said field effect transistor is formed, and subsequently etching said third semiconductor layer (1 4 ) exposed at said gate region using said fourth semiconductor layer (15) exposed at source and drain regions as a mask, thereby isolating source and drain layers (14 2 , 14 3 ) of said third semiconductor layer (14), forming source and drain electrodes (21 1 , 21 2 ) respectively on said source and drain layers (142, 14 3 ) with a high impurity concentration, and forming a gate electrode (22) on said first semiconductor layer (12) between said source and drain layers (14 2 , 14 3 ) with a high impurity concentration.
Claim 11
Independent Claim
381 words
A method of manufacturing an opto-electronic integrated circuit device in which a light-emitting device and a field effect transistor are integrated on a substrate, comprising the steps of growing a first semiconductor layer (12), serving as a channel layer of a field effect transistor, on a semi-insulating semiconductor substrate (11), growing a second semiconductor layer (13), serving as an etching stopper layer and made of a material different from that of said first semiconductor layer (12) on said first semiconductor layer (12), growing a third semiconductor layer (14), serving as a first clad layer (14 1 ) of said light-emitting device and source and drain layers (14 2 , 14 3 ) with a high impurity concentration of said field effect transistor and made of a material different from that of said second semiconductor layer (13), on said second semiconductor layer (13), growing a fourth semiconductor layer (15) serving as an active layer (15 1 ) of said light-emitting device , and an etching mask (15 2 , 15 3 ) used when a gate region of said field effect transistor is recess-etched and made of a material different from that of said third semiconductor layer (14), selectively etching a region around said active layer (15 1 ) of said light-emitting device and said gate region of said field effect transistor of said fourth semiconductor layer (15), sequentially growing a fifth semiconductor layer (17) serving as a second clad layer of said light-emitting device and a sixth semiconductor layer (18) serving as a cap layer, selectively etching a region of said sixth and fifth semiconductor layers (18, 17) characterized in that said field effect transistor is formed, and subsequently etching said third semiconductor layer (1 4 ) exposed at said gate region using said fourth semiconductor layer (15) exposed at source and drain regions as a mask, thereby isolating source and drain layers (14 2 , 14 3 ) of said third semiconductor layer (14), forming source and drain electrodes (21 1 , 21 2 ) respectively on said source and drain layers (142, 14 3 ) with a high impurity concentration, and forming a gate electrode (22) on said first semiconductor layer (12) between said source and drain layers (14 2 , 14 3 ) with a high impurity concentration.
Claim 12
Dependent Claim
89 words
A method according to claim 8, characterized in that said semi-insulating semiconductor substrate (11) is an InP substrate, said first semiconductor layer (12) is an n-type InP layer, said secono semiconductor layer (13) is a GaInAsP layer or a GaInAs layer, said third semiconductor layer (14) is an n-type InP layer, said fourth semiconductor layer (15) is a GaInAsP layer or a GaInAs layer, said fifth semiconductor layer (17) is a p-type InP layer, and said sixth semiconductor layer (18) is a p-type GaInAsP layer or a GaInAs layer.
Claim 13
Dependent Claim
36 words
A method according to claim 8, characterized in that said field effect transistor is a Schottky gate field effect transistor in which a Schottky barrier is formed between said gate electrode (22) and said channel layer.
Claim 14
Dependent Claim
21 words
A method according to claim 8, characterized in that said light-emitting device is a laser diode having a double heterojunction structure.