Ceramic wiring substrate and method of forming it

Claim 2

A ceramic wiring substrate comprising at least one layer of a signal line pattern, a ground electrode pattern layer, and a cavity formed by a region which covers part of or completely said signal line pattern inside ceramic between said signal line pattern and said ground electrode pattern.

Claim 3

A substrate according to claim 1, wherein said cavity is formed by forming a cavity pattern consisting of a material which is decomposed and scattered at a sintering temperature or less of a green sheet of said ceramic on said green sheet of ceramic, sandwiching said cavity pattern between said line pattern layer and said ground electrode pattern layer, heating and pressing said cavity pattern layer to obtain a stacking body between said line pattern layer and said ground electrode pattern layer, and gradually heating said stacking body in an oxidizing atmosphere so that said material which forms said cavity pattern is decomposed and removed.

Claim 4

A substrate according to claim 2, wherein said cavity pattern is formed by printing a carbon paste on said ceramic green sheet.

Claim 5

A substrate according to claim 2, wherein said cavity pattern is obtained by stacking a cavity formation layer having a through hole at a portion in which said cavity is to be formed and a sheet without a hole, forming a composite sheet so that said hole portion becomes a groove, and charging a carbon paste in said groove of said composite sheet.

Claim 6

A substrate according to claim 2, wherein said cavity pattern is formed by forming a photosensitive resin film on a carrier film, forming a cavity pattern using a photo mask, pressing said cavity pattern against a ceramic green sheet, and removing said carrier film.

Claim 7

A ceramic wiring substrate wherein a plurality of pads for connecting memory chips are formed on its surface and signal lines and ground electrodes most of which are arranged parallel to each other are formed therein, comprising a plurality of layers of cavities formed in a ceramic portion between said signal lines and said ground electrodes and parallel to each of said signal lines so that a width of each of said cavities is greater than that of said signal line.

Claim 8

A ceramic wiring substrate wherein a plurality of pads for connecting memory chips are formed on its surface and signal lines and ground electrodes most of which are arranged parallel to each other are formed therein, comprising a plurality of layers of cavities formed in a ceramic portion between said signal lines and said ground electrodes and parallel to each of said signal lines so that a width of each of said cavities is greater than that of said signal line.

Claim 9

A substrate according to claim 6, wherein the width of said signal line is on the order of 150 µm or less, the width of each of said cavities is about three times that of said signal line and its thickness is on the order of about 10 µm, thereby reducing the capacitance relative to ground by about 600/0 as compared with the case in which no cavity is formed.