Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
108 words
In a cellular array of the type employing a plurality of processors arranged in a matrix of rows and columns wherein each processor in said array can communicate with other processors to the left and right and up and down in the horizontal and vertical directions to perform arithmetic operations, the improvement therewith comprising: a plurality of said processors (200 to 219) arranged in a row with at least two of said processors in said row operative to generate address information; and separate memory means (220 to 239), each said separate memory means being coupled to said two processors in said row to receive said address information generated.
Claim 2
Dependent Claim
108 words
In a cellular array of the type employing a plurality of processors arranged in a matrix of rows and columns wherein each processor in said array can communicate with other processors to the left and right and up and down in the horizontal and vertical directions to perform arithmetic operations, the improvement therewith comprising: a plurality of said processors (200 to 219) arranged in a row with at least two of said processors in said row operative to generate address information; and separate memory means (220 to 239), each said separate memory means being coupled to said two processors in said row to receive said address information generated.
Claim 3
Dependent Claim
19 words
The cellular array according to Claim 1, wherein each said separate memory is a Dynamic Random Access Memory (DRAM).
Claim 4
Dependent Claim
18 words
The cellular array according to Claim 1, wherein said at least two processors are adjacent in said row.
Claim 5
Dependent Claim
56 words
The cellular array according to Claim 1, wherein said processors in said row are connected to a common bus (250) accommodating a given number of bits, with an address decoder means coupled to said bus to enable said two processors to couple to said decoder via said bus to select any other processors in said row.
Claim 6
Dependent Claim
43 words
The cellular array according to Claim 4, wherein said address decoder means includes a row decoder (240) coupled to said memory means associated with each processor to select said memory means by employing a first lesser number of bits than said given number.
Claim 7
Dependent Claim
42 words
The cellular array according to Claim 5, wherein said address decoder means includes a column decoder coupled to said memory means and operative to select a processor in a column by employing a second lesser number of bits from said given number.
Claim 8
Dependent Claim
33 words
The cellular array according to Claim 1, wherein each processor includes logic means (301) for storing therein address data for determining which processors in said row are selected to provide said address generation.
Claim 9
Dependent Claim
37 words
The cellular array according to Claim 7, wherein any two of said plurality of processors in said row can be selected to provide said address generation with other processors in said row operative to provide arithmetic operations.
Claim 10
Dependent Claim
15 words
The cellular array according to Claim 7, wherein said logic means includes a multiport RAM.
Claim 11
Dependent Claim
23 words
The cellular array according to Claim 4, further including means (242) coupled to said bus for transferring data to said address generating processors.
Claim 12
Dependent Claim
15 words
The cellular array according to Claim 1, wherein each said processor is a 16-bit processor.
Claim 13
Dependent Claim
16 words
The cellular array according to Claim 4, wherein said common bus accommodates 32 bits of data.
Claim 14
Dependent Claim
33 words
The cellular array according to Claim 4, with a first given number of bits operative to determine a row address and a second given number of bits operative to determine a column address.
Claim 15
Dependent Claim
18 words
The cellular array according to Claim 13, wherein said first and second given number of bits is eight.