EP0231948A2
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Simulation system
Assignee: Aida Corp
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Filing: 1987-02-06
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Granted: —
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Expires: 2007-02-06
Abstract
Abstract A levelized simulation system includes a means for storing a model of a logic system to be simulated. The logic system has a plurality of levels of logic which are synchronously clocked. A processing system (l9) includes an arithmetic logic unit (3l) which sequentially tests each element of said logic system, one level of logic at a time. Thus each logic element in the first level is tested with the results there stored in a state memory (2l), after which the logic elements of the second level of the logic system are tested and so on. During each test a comparison is made to determine whether there is a defect in the logic design.
Inventors
- 👤 Michael W. Samuels
- 👤 John J. Zasio
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 10:16
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
93 words
A method for simulating a logic system which has multiple levels of logic elements, characterized in that a model of the logic system to be simulated is stored in memory (ll); each logic element at each logic level in the model is evaluated at successive levels in sequence; an output of the evaluation of each logic element in each level is stored; succeeding levels of logic elements are evaluated in response to the stored model and said stored outputs; and an indication is provided upon determination of a defect in the logic system.
Claim 2
Independent Claim
93 words
A method for simulating a logic system which has multiple levels of logic elements, characterized in that a model of the logic system to be simulated is stored in memory (ll); each logic element at each logic level in the model is evaluated at successive levels in sequence; an output of the evaluation of each logic element in each level is stored; succeeding levels of logic elements are evaluated in response to the stored model and said stored outputs; and an indication is provided upon determination of a defect in the logic system.
Claim 3
Independent Claim
142 words
A method according to claim l, characterized in that the model of the logic system to be simulated is stored in an instruction memory (ll); the initialized state of the first level of logic of the logic system is initially stored in a state memory (2l); outputs corresponding to the input states of succeeding levels of logic are subsequently stored; instructions corresponding to each logic element in each level of logic in the logic system are read from the instruction memory (ll) in a level by level sequence; the stored conditions of a corresponding one of each of said logic elements are sequentially read from said state memory (2l); and a logic operation is performed and the output thereof is stored in response to instructions corresponding to each logic element and in response to the stored input states for each logic element.
Claim 4
Dependent Claim
224 words
Apparatus for simulating a logic system having a plurality of levels of logic in accordance with claim l characterized by an instruction memory (ll) for storing the logic system to be simulated; a state memory (2l) for initially storing the initialized state of a first level of logic of the logic system and for storing subsequent outputs for an evaluated simulated logic element; read circuitry (39) for subsequently reading instructions from the instruction memory (ll) in a level by level sequence corresponding to each logic element in each level of logic in the logic system; a circuit (45) responsive to the read circuitry (39) for sequentially reading the stored conditions of a corresponding one of each of the logic elements from the state memory (2l); arithmetic logic circuitry (3l) for receiving from the state memory (2l) the stored conditions for logic elements and the instructions from the instruction memory (ll) corresponding to each of the logic elements for generating an output for storage in the state memory (2l) corresponding to the function of each of the logic elements, the arithmetic logic circuitry sequentially performing a logic function for each logic element in a level of logic system and repeatedly generating outputs for each succeeding level of logic of the logic system; and recording circuitry for recording the defects in said logic system being simulated.
Claim 5
Dependent Claim
57 words
Apparatus according to claim 3, characterized in that said instruction memory (ll) stores a set of instructions which comprise the logic system being simulated, each instruction corresponding to a logic element of the logic system being simulated, and the instructions being ordered in the state memory in accordance with the level of logic of said logic system.
Claim 6
Dependent Claim
56 words
Apparatus according to claim 4, characterized in that each of the instructions comprises a data word having therein the address in the state memory (2l) of the input state of the corresponding logic element, and an operation code for causing the arithmetic logic circuitry to generate an output corresponding to the function of the logic element.
Claim 7
Dependent Claim
30 words
Apparatus according to claim 5, characterized in that the state memory (2l) stores a plurality of words each comprising two bits to identify an input state to a logic element.
Claim 8
Dependent Claim
24 words
Apparatus according to claim 6, characterized by circuitry (l3) for transmitting and receiving data between the state memory (2l) and a remote computer (l7).
Claim 9
Dependent Claim
29 words
Apparatus according to claim 7, characterized in that address locations in the instruction memory (ll) are sequentially addressed in response to instruction words being written thereto or accessed therefrom.
References Cited (Backward Citations)
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