Vector pattern processing circuit for bit map display system

Claim 1

A vector pattern processing circuit for a bit map display system including a display unit having a plurality of quasi regions in a matrix form defined in a plane of said display unit each forming N × N dots, comprising: first and second memory units each including a plurality of words formed in a matrix, each word having an N × N bits structure, said words in said first memory unit corresponding to diagonal quasi regions of said display unit and said words in said second memory unit corresponding other diagonal quasi regions of said display unit; first and second word register units, operatively connected to said first and second memory units, each having an N × N bits structure; a vector pattern generation circuit receiving start and end coordinates in said quasi regions defining a processing vector pattern, and generating a first dot data of a primary axis for said vector pattern and a second dot data of a subsidiary axis perpendicular to said primary axis in response to a gradient of said vector pattern with respect to said primary axis along said primary axis for every N dots in said primary axis; a bit setting circuit, operatively connected between said first and second word register units and said vector pattern generation circuit, energizing one of said first and second word register units in response to said first and second dot data from said vector pattern generation circuit, and setting a bit defined by said first and second dot data to said energized word register unit in each dot data generation time at said vector pattern generation circuit; and a store control circuit, operatively connected to said first and second memory units and said vector pattern generation circuit, receiving said start coordinate and addressing at least one address of a word in one of said memory units defined by said start coordinate, so that at least one data set, in one of said word register units is stored in said word defined by said address.