EP0230154A2
Expired / Lapsed
EP
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Integrated circuit structures comprising current busses
Assignee: Advanced Micro Devices Inc
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Filing: 1986-12-31
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Granted: —
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Expires: 2006-12-31
Abstract
Abstract An improved integrated circuit structure is disclosed which comprises a Vcc bus and a Vss bus having capacitance means coupled between the busses and distributed along the length of the busses to reduce the voltage spikes induced during switching. In a preferred embodiment, the capacitance means comprise one or more capacitors formed beneath one of the busses. Construction of MOS capacitors beneath one or more of the busses is disclosed.
Inventors
- 👤 Bharat Dahyabhai Patel
- 👤 Stephen Y. Tam
- 👤 Pravin R. Shah
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 16:50
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/495; H10D; H10D84/00; H10D84/201; H10D84/204; H10D84/212; H10W20/41; H10W20/427; H10D89/00; H10D89/211; H10D89/213
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
33 words
An improved integrated circuit structure including current busses, said improvement comprising capacitance means coupled between the busses and distributed along the length of the busses to compensate for inductance present in the structure.
Claim 2
Dependent Claim
33 words
An improved integrated circuit structure including current busses, said improvement comprising capacitance means coupled between the busses and distributed along the length of the busses to compensate for inductance present in the structure.
Claim 3
Dependent Claim
25 words
The improved integrated circuit structure of claim 1 wherein said capacitance means comprises one or more capacitors formed beneath at least one of the busses.
Claim 4
Dependent Claim
18 words
The improved integrated circuit structure of claim 2 wherein said capacitance means comprise one or more MOS capacitors.
Claim 5
Dependent Claim
52 words
The improved integrated circuit structure of claim 3 wherein said MOS capacitor comprises an MOS device having a gate electrode electrically connected to one of said busses and forming one electrode of said capacitor and the channel formed in said structure beneath the gate electrode comprises the other electrode of said capacitor.
Claim 6
Dependent Claim
26 words
The integrated circuit structure of claim 4 wherein said channel is electrically connected to said other bus through either the source or drain electrodes or both.
Claim 7
Dependent Claim
30 words
The integrated circuit structure of claim 4 wherein the amount of capacitance is adjusted by varying the thickness of the gate oxide separating the gate electrode from the underlying channel.
Claim 8
Dependent Claim
52 words
The integrated circuit structure of claim 4 wherein said gate electrode under said bus is divided into a plurality of segments and each of said segments is independently connected electrically at a spaced apart point to one of said busses to thereby form a plurality of parallel capacitors distributed along said busses.
Claim 9
Dependent Claim
27 words
The integrated circuit structure of claim 7 wherein insulating means are provided to isolate each of said adjacent gate electrode segments in said structure from one another.
Claim 10
Dependent Claim
46 words
The integrated circuit structure of claim 2 wherein said capacitance means comprise a first conductive member formed adjacent a first bus on said structure and electrically coupled to a second bus on said structure, and dielectric means separating said first conductive member and said first bus.
Claim 11
Dependent Claim
33 words
The integrated circuit structure of claim 9 wherein the capacitance of said capacitance means is adjusted by varying the thickness of said dielectric means between said first bus and said first conductive member.
Claim 12
Dependent Claim
53 words
The integrated circuit structure of claim 9 wherein said first conductive member adjacent said first bus is divided into a plurality of segments and each of said segments is independently connected electrically at a spaced apart point to said second bus to thereby form a plurality of parallel capacitors distributed along said busses.
Claim 13
Dependent Claim
136 words
An improved integrated circuit structure comprising: (a) a first current bus and a second bus biased at a voltage level spaced from said first bus; (b) capacitance means formed beneath at least one of said busses comprising an MOS capacitor having a gate electrode forming a first plate of said capacitance means and electrically connected to one of said busses; (c) channel means formed in said structure beneath said gate electrode comprising the opposite plate of said capacitance means and separated from said gate electrode by gate oxide means; and (d) a second electrode connecting said channel means of said MOS capacitor to the other of said busses; whereby inductance voltages induced in said busses during switching will be compensated for by said capacitance means to thereby reduce the voltage spikes produced by said induced voltages.
Claim 14
Dependent Claim
136 words
An improved integrated circuit structure comprising: (a) a first current bus and a second bus biased at a voltage level spaced from said first bus; (b) capacitance means formed beneath at least one of said busses comprising an MOS capacitor having a gate electrode forming a first plate of said capacitance means and electrically connected to one of said busses; (c) channel means formed in said structure beneath said gate electrode comprising the opposite plate of said capacitance means and separated from said gate electrode by gate oxide means; and (d) a second electrode connecting said channel means of said MOS capacitor to the other of said busses; whereby inductance voltages induced in said busses during switching will be compensated for by said capacitance means to thereby reduce the voltage spikes produced by said induced voltages.
Claim 15
Independent Claim
44 words
A method of making an improved integrated circuit structure having means for inhibiting induced voltage spikes during switching in current busses in said structure which comprises: forming capacitance means in said structure coupled to said busses and distributed along the length of said busses.
Claim 16
Independent Claim
44 words
A method of making an improved integrated circuit structure having means for inhibiting induced voltage spikes during switching in current busses in said structure which comprises: forming capacitance means in said structure coupled to said busses and distributed along the length of said busses.
Claim 17
Dependent Claim
34 words
The method of claim 13 wherein the step of forming capacitance means in said structure comprises forming said capacitance means adjacent at least one of said busses and separated therefrom by a dielectric layer.
Claim 18
Dependent Claim
34 words
The method of claim 14 wherein the step of forming capacitance means in said structure adjacent at least one of said busses comprises forming said capacitance means beneath at least one of said busses.
Claim 19
Dependent Claim
43 words
The method of claim 15 including the further steps of forming a first conductive layer beneath said bus, forming an insulating layer above said conductive layer, and connecting said conductive layer to a second bus to form a capacitance means between said busses.
Claim 20
Dependent Claim
43 words
The method of claim 15 which includes the further steps of separating said conductive layer into a plurality of regions and independently connecting each of said regions to said second bus to thereby provide a plurality of capacitance means distributed along said bus.
Claim 21
Dependent Claim
51 words
The method of claim 17 which includes the further steps of forming a conductive area in said structure beneath said conductive layer, forming a second insulating layer over said conductive area to electrically separate said conductive area from said conductive layer, and electrically connecting said conductive area to said first bus.
Claim 22
Dependent Claim
93 words
The method of claim 15 including the further steps of: (a) forming a conductive area in said structure beneath one of said busses; (b) forming an insulating layer over at least a portion of said conductive area; (c) forming a conductive layer over said insulating layer beneath said bus comprising a gate electrode; (d) forming an insulating layer above said gate electrode; and (e) connecting said conductive area in said structure to one of said busses and connecting said gate electrode to another of said busses to thereby provide capacitance between said busses.
Claim 23
Independent Claim
117 words
A method of making an improved integrated circuit structure having means for inhibiting induced voltages during switching in current busses in said structure which comprises: (a) doping said structure to form a conductive channel area in said structure beneath one of said busses and extending for substantially the length of said bus; (b) forming a gate oxide layer over at least a portion of said channel area; (c) forming a gate electrode over said gate oxide layer; (d) forming an insulating layer above said gate electrode; and (e) connecting said channel layer in said structure to one of said busses and connecting said gate electrode to another of said busses to thereby provide capacitance between said busses.
Claim 24
Independent Claim
117 words
A method of making an improved integrated circuit structure having means for inhibiting induced voltages during switching in current busses in said structure which comprises: (a) doping said structure to form a conductive channel area in said structure beneath one of said busses and extending for substantially the length of said bus; (b) forming a gate oxide layer over at least a portion of said channel area; (c) forming a gate electrode over said gate oxide layer; (d) forming an insulating layer above said gate electrode; and (e) connecting said channel layer in said structure to one of said busses and connecting said gate electrode to another of said busses to thereby provide capacitance between said busses.
Claim 25
Dependent Claim
47 words
The method of claim 20 which includes the further step of forming source and drain regions in said structure adjacent said channel area and electrically connecting said channel area to one of said busses through one or more electrodes connected to said said source and drain regions.
Claim 26
Dependent Claim
46 words
The method of claim 21 which includes the further steps of separating said gate electrode into a plurality of regions and independently connecting each of said gate electrode regions to one of said busses to thereby provide a plurality of capacitance means distributed between said busses.
Claim 27
Dependent Claim
24 words
The method of claim 21 including the further step of adjusting the thickness of said gate oxide to vary the capacitance between said busses.
References Cited (Backward Citations)
No citation records indexed.
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