Semiconductor device and method of fabrication

Claim 2

A process of fabricating a semiconductor device of improved electrical ruggedness on a wafer of semiconductor material, said wafer comprising a substrate and a wafer layer thereon containing a first type of dopant, said process comprising the steps of: forming a first insulating layer on a major surface of said wafer layer; forming on the exposed surface of said first insulating layer an electrode layer of refractory material having a first window exposing said first insulating layer; introducing a second type of dopant through said first window and through said insulating layer to form a first region of predetermined depth in said wafer layer; forming a first mask layer at least over said first window including the walls thereof; opening a second window between the walls of said first window, said second window extending through said first mask layer and through said first insulating layer to expose said major surface; introducing said second type of dopant through said second window to form a second region in said wafer layer having a depth greater than said first region; . forming a second mask layer on said major surface within said second window; removing at least said first mask layer and a portion of said first insulating layer to open a third window, said third window extending between the walls of said first window and said second mask layer to expose a portion of said major surface therebetween; introducing said first type of dopant through said third window to from a third region in said water layer of lesser depth than said first region ; forming a second insulating layer on said last-recited exposed portion of said major surface and on the exposed surfaces of said electrode layer, said first insulating layer, and said second mask layer, respectively; removing said second mask layer and substantially all of said second insulating layer within said first window, said last-recited removal step retaining said second insulating layer on said first window walls to define a fourth window therebetween, said fourth window exposing a portion of said major surface including portions of said second and third, regions; and forming a metallized electrode in ohmic contact with said exposed portions of said second and third regions and extending out of said fourth window; whereby a high surface dopant concentration level is obtained for said second region.

Claim 3

The method of claim 1 wherein a third insulating layer is formed on said refractory electrode layer following formation of the latter; and removing said third insulating layer during the step of opening sald third window.

Claim 4

The method according to claim 1 wherein said first mask layer comprises silicon nitride.

Claim 5

The method according to claim 1 wherein the step of forming said second mask layer comprises growing said layer by thermal oxidation of said wafer material.

Claim 6

The method according to claim 1 wherein said firsr region is formed in said wafer layer by ion implantation of said second type of dopant and by subsequent heating.

Claim 7

The method according to claim 5 wherein said first and second types of dopants are N-type and P-type materials respectively.

Claim 8

The method according to claim 5 wherein said first and second types of dopants are P-type and N-type materials respectively.

Claim 9

The method according to claim 6 wherein said semiconductor wafer material comprises silicon.

Claim 10

The method according to claim 8 wherein the step of forming said second mask layer comprises growing said layer by thermal oxidation of said wafer material.

Claim 11

A semiconductor device having improved _ electrical ruggedness comprising: a wafer of semiconductor material; said wafer including a substrate and a drift region of a first conductivity type thereon, said drift region having a major surface; a base region of a second conductivity type in said drift region and forming a P-N junction therewith, said base region having a deep portion with a dopant concentration at least as high as 5×10 19 atoms per cubic centimeter; an emitter region of said first conductivity type in said base region, each of said drift, base and emitter regions sharing a portion of said major surface; and a gate electrode for inducing a channel region at said major surface in said base region between said emitter and drift regions.

Claim 12

A semiconductor device having improved _ electrical ruggedness comprising: a wafer of semiconductor material; said wafer including a substrate and a drift region of a first conductivity type thereon, said drift region having a major surface; a base region of a second conductivity type in said drift region and forming a P-N junction therewith, said base region having a deep portion with a dopant concentration at least as high as 5×10 19 atoms per cubic centimeter; an emitter region of said first conductivity type in said base region, each of said drift, base and emitter regions sharing a portion of said major surface; and a gate electrode for inducing a channel region at said major surface in said base region between said emitter and drift regions.

Claim 13

A semiconductor device according to claim 10 and further comprising a metallized electrode in ohmic contact with said emitter region and electrically connecting the latter with said base region at a location on said major surface spaced from said channel region.

Claim 14

A semiconductor device according to claim 11 1 wherein said substrate comprises a collector region of said second conductivity type adjacent said drift region and spaced from said major; surface.

Claim 15

A semiconductor device having a deep base portion with a dopant concentration at least as high as 5×10 19 atoms per cabic centimeter, said device including wafer of semiconductor material, said wafer comprising a substrate and a wafer layer thereon containing a first type of dopant and being fabricated by the steps of: forming a first insulating layer on a major surface of said wafer layer; forming an electrode layer of refractory material on the exposed surface of said first insulating layer; opening a first window in said electrode layer to expose said first insulating layer; introducing a second type of dopant into said wafer through said first window and through said insulating layer to form a first region of predetermined depth in said wafer layer; forming a first mask layer at least over said first window including the walls thereof; opening a second window between the walls of said first window, said second window extending through said first mask layer and through said first insulating layer to expose said major surface; introducing said second dopant type through said second window to form a second region in said wafer layer comprising said deep base portion and having a depth greater than said first region; forming a second mask layer on said major surface within said second window; removing at least said first mask layer and a portion of said first insulating layer to open a third window, said third window extending between the walls of said first window and said second mask layer to expose a portion of said major surface therebetween; introducing said first type of dopant through said third window to form a third region in said wafer layer of lesser depth than said first region; forming a second insulating layer on said last-recited exposed partion of said major surface and on the exposed surfaces of said electrode layer, said first insulating layer, and said second mask layer, respectively; removing said second mask layer and substantially all of said second insulating layer within said first window, said last-recited removal step retaining said second insulating layer on said first window walls to define a fourth window therebetween, said fourth window exposing a portion of said major surface including portions of said second and third regions ; and forming a metallized electrode in ohmic contact with said exposed portions of said second and third regions and extending out of said fourth window.

Claim 16

A semiconductor device having a deep base portion with a dopant concentration at least as high as 5×10 19 atoms per cabic centimeter, said device including wafer of semiconductor material, said wafer comprising a substrate and a wafer layer thereon containing a first type of dopant and being fabricated by the steps of: forming a first insulating layer on a major surface of said wafer layer; forming an electrode layer of refractory material on the exposed surface of said first insulating layer; opening a first window in said electrode layer to expose said first insulating layer; introducing a second type of dopant into said wafer through said first window and through said insulating layer to form a first region of predetermined depth in said wafer layer; forming a first mask layer at least over said first window including the walls thereof; opening a second window between the walls of said first window, said second window extending through said first mask layer and through said first insulating layer to expose said major surface; introducing said second dopant type through said second window to form a second region in said wafer layer comprising said deep base portion and having a depth greater than said first region; forming a second mask layer on said major surface within said second window; removing at least said first mask layer and a portion of said first insulating layer to open a third window, said third window extending between the walls of said first window and said second mask layer to expose a portion of said major surface therebetween; introducing said first type of dopant through said third window to form a third region in said wafer layer of lesser depth than said first region; forming a second insulating layer on said last-recited exposed partion of said major surface and on the exposed surfaces of said electrode layer, said first insulating layer, and said second mask layer, respectively; removing said second mask layer and substantially all of said second insulating layer within said first window, said last-recited removal step retaining said second insulating layer on said first window walls to define a fourth window therebetween, said fourth window exposing a portion of said major surface including portions of said second and third regions ; and forming a metallized electrode in ohmic contact with said exposed portions of said second and third regions and extending out of said fourth window.