EP0228624A2
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EP
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Field effect transistor
Assignee: Sumitomo Electric Industries Ltd
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Filing: 1986-12-09
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Granted: —
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Expires: 2006-12-09
Abstract
Abstract A field effect transistor utilizing semiconductor hetero junction with high mutual conductance as well as low noise with source resistance reduced comprises a gallium indium arsenide mixed crystal semiconductor layer (23) providing a current path, indium phosphide layers (22, 34) capable of making easily low resistance formed on or under the gallium indium arsenide mixed crystal semiconductor layer (23) by ion-implantation, a source electrode (6), a gate electrode (5) and a drain electrode (7) which are formed on the surface of an aluminum indium arsenide mixed crystal semiconductor layer (24) formed on an uppermost layer, and an ion-implanted layer formed at least in a region to form a source resistance between the source electrode (6) and two-dimensional electron layer (8) within the gallium indium arsenide mixed crystal semiconductor layer (23).
Inventors
- 👤 Goro Osaka Works Of Sumitomo Sasaki
- 👤 Hideki Osaka Works Of Sumitomo Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 17:54
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/4732; H10D30/475; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1404; H10P32/1406
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
166 words
A field effect transistor utilizing semiconductor hetero junction, comprising: a semi-insulating substrate (21); a gallium indium arsenide (Ga In As) mixed crystal semiconductor layer (23) formed on said semi-insulating substrate (21), having a current path formed therein; a first layer formed on said Ga In As mixed crystal semiconductor layer (23), including at least an aluminum indium arsenide (Al In As) mixed crystal semiconductor layer (24); indium phosphide (In P) layers (22, 34) disposed on or under said Ga In As mixed crystal semiconductor layer (23); a gate electrode (5) formed in a predetermined region on the surface of said Al In As mixed crystal semiconductor layer (24), a source electrode (6) and a drain electrode (7) provided opposed to each other on respective sides of said gate electrode (5), and ion-implanted layers (25, 25') formed by implanting impurity ions at least into a region between said gate electrode (5) and said source electrode (6) and between said gate electrode (5) and said drain electrode (7).
Claim 2
Dependent Claim
166 words
A field effect transistor utilizing semiconductor hetero junction, comprising: a semi-insulating substrate (21); a gallium indium arsenide (Ga In As) mixed crystal semiconductor layer (23) formed on said semi-insulating substrate (21), having a current path formed therein; a first layer formed on said Ga In As mixed crystal semiconductor layer (23), including at least an aluminum indium arsenide (Al In As) mixed crystal semiconductor layer (24); indium phosphide (In P) layers (22, 34) disposed on or under said Ga In As mixed crystal semiconductor layer (23); a gate electrode (5) formed in a predetermined region on the surface of said Al In As mixed crystal semiconductor layer (24), a source electrode (6) and a drain electrode (7) provided opposed to each other on respective sides of said gate electrode (5), and ion-implanted layers (25, 25') formed by implanting impurity ions at least into a region between said gate electrode (5) and said source electrode (6) and between said gate electrode (5) and said drain electrode (7).
Claim 3
Dependent Claim
61 words
A field effect transistor in accordance with claim 1, wherein said In P layer (22) is formed between said Ga In As mixed crystal semiconductor layer (23) and said semi-insulating substrate (21), contacting said Ga In As mixed crystal semiconductor layer (23), and said first layer comprises by a single layer of said Al In As mixed crystal semiconductor layer (24).
Claim 4
Dependent Claim
27 words
A field effect transistor in accordance with claim 2, wherein said ion-implanted layer (25) is formed to the depth reaching at least said In P layer (22).
Claim 5
Dependent Claim
21 words
A field effect transistor in accordance with claim 2, wherein said In P layer (22) is approximately 1 µm in thickness.
Claim 6
Dependent Claim
34 words
A field effect transistor in accordance with claim 2, wherein said In P layer (22) is formed as an n-type layer having doped impurities of less than 10 15 / cm 3 in concentration.
Claim 7
Dependent Claim
33 words
A field effect transistor in accordance with claim 2, wherein said In P layer (22) is formed as a p- type layer having doped impurities of 10 16 / cm 3 in concentration.
Claim 8
Dependent Claim
38 words
A field effect transistor in accordance with claim 2, wherein said Al In As mixed crystal semiconductor layer (24) is formed as an n-type layer having doped impurities of the order of 10 18 /cm 3 in concentration.
Claim 9
Dependent Claim
44 words
A field effect transistor in accordance with claim 2, wherein said ion-implanted layer (25) is an n-type layer in which n-type impurities are implanted under the condition of acceleration voltage of 100 keV and a dose of more than 10 14 /cm 2 .
Claim 10
Dependent Claim
57 words
A field effect transistor in accordance with claim 1, wherein said first layer (39) comprises an indium phosphide (In P) layer (34) formed on the surface of said Ga In As mixed crystal semiconductor layer (23) and a first Al In As mixed crystal semiconductor layer (24) formed on the surface of said In P layer (34).
Claim 11
Dependent Claim
52 words
A field effect transistor in accordance with claim 9, which further comprises a second aluminum indium arsenide (Al In As) mixed crystal semiconductor layer (32) formed between said semi-insulating substrate (21) and said Ga In As mixed crystal semiconductor layer (23), contacting said Ga In As mixed crystal semiconductor layer (23) .
Claim 12
Dependent Claim
48 words
A field effect transistor in accordance with claim 9, which further comprises a third aluminum indium arsenide (Al 'In As) mixed crystal semiconductor layer (40) formed between said Ga In As mixed crystal semiconductor layer (24) and said In P layer (34), contacting said both layers (23, 24).
Claim 13
Dependent Claim
32 words
A field effect transistor in accordance with claim 9, wherein said ion-implanted layer (25') is formed to the depth reaching the interior of said Ga In As mixed crystal semiconductor layer (23).
Claim 14
Dependent Claim
42 words
A field effect transistor in accordance with claim 9, wherein at least said Ga In As mixed crystal semiconductor layer (23), said In P layer (34) and said first Al In As mixed crystal semiconductor layer (24) all include no doped impurities.
Claim 15
Dependent Claim
34 words
A field effect transistor in accordance with claim 9, wherein said In P layer (34) is formed under the condition of n-type impurities doped of the order of 10 1 8/cm 3 in concentration.
Claim 16
Dependent Claim
39 words
A field effect transistor in accordance with claim 14, wherein said In P layer (34) includes a non-doped region in the range of approximately 10 nm from the surface contacting said Ga In As mixed crystal semiconductor layer (23).
Claim 17
Dependent Claim
48 words
A field effect transistor in accordance with claim 12, wherein said ion-implanted layer (25') is an n-type layer in which n-type impurity ions are implanted under the condition of an acceleration voltage of more 14 2 than 100 KeV and a dose of more than 10 /cm .
References Cited (Backward Citations)
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