Programmable sharing of display memory between update and display processes in a raster scan video controller

Claim 2

A logical subsystem for programmable sharing of access to a memory in a computer system having a plura­lity of systems resources for use in processing data, said access times to be shared among two or more processes, comprising: a memory having one or more signals on which data can be read or written; two or more processing devices each having a number of signals by means of which they read or write data; programmable means to assign a priority to each of said processing devices; programmable means to assign a percentage of the available memory accesses in a time period to each of said processing devices; control means to process a resource request from each of said processing devices requesting access to said memory; control means to grant a resource request from each of said processing devices for use in accessing said memory; programmable means to allocate said resources and said access times among said devices according to said programmable priorities and percentages; first means to terminate a series of memory accesses based on a signalled event; second means to terminate a series of memory accesses based on a programmed time limit for the device performing said accesses; Programmable means to control whether said first termination means or said second termination means prevails for a given access.

Claim 3

A circuit for programmable sharing of a plurality of system resources for use in processing operations in a computer system, said resources to be shared between update and display processes in a raster scan video controller, comprising: a display memory having one or more signals on which data can be read or written; two or more processing devices, each having a number of signals on which they read or write data; a raster scan video display; means to read out selected contents of said display memory and to transform said contents to the signalling necessary to control the raster scan beam of a video display in active display time; means to provide horizontal and vertical retrace signalling at appropriate intervals to said raster scan video display, and means to blank the raster scan beam during retrace; programmable means to assign a priority to each of the processing devices; means for each processing device to request system resources to access and display data; means to grant said resource requests; programmable means to allocate said system resources among said processing devices according to said priority assignment; first means to terminate a series of display memory accesses based on a signalled event; second means to terminate a series of display memory accesses based on a count of said accesses for the device performing them; means to control whether said first termination means or said second termination means prevails for a given display memory access.

Claim 4

A circuit for programmable sharing of a plurality of system resources for use in processing operations in a computer system, said resources to be shared between update and display processes in a raster scan video controller, comprising: a display memory having one or more signals on which data can be read or written; two or more processing devices, each having a number of signals on which they read or write data; a raster scan video display; means to read out selected contents of said display memory and to transform said contents to the signalling necessary to control the raster scan beam of a video display in active display time; means to provide horizontal and vertical retrace signalling at appropriate intervals to said raster scan video display, and means to blank the raster scan beam during retrace; programmable means to assign a priority to each of the processing devices; means for each processing device to request system resources to access and display data; means to grant said resource requests; programmable means to allocate said system resources among said processing devices according to said priority assignment; first means to terminate a series of display memory accesses based on a signalled event; second means to terminate a series of display memory accesses based on a count of said accesses for the device performing them; means to control whether said first termination means or said second termination means prevails for a given display memory access.

Claim 5

The distribution logic of Claim 1 or 2 wherein said first means to terminate a series of memory accesses is based on a signal that a process has reached a termina­tion point.

Claim 6

The distribution logic of Claim 2 wherein said first means to terminate a series of memory accesses is based on a signal indicating that a raster scan has reached the end of a scan line.

Claim 7

The distribution logic of Claim 1 or 2 wherein said first means to terminate a series memory accesses is based on a signal indicating that a memory output buffer is full.

Claim 8

The distribution logic of Claim 1 or 2 wherein said second means to terminate an access is based on the expiration of a count of said accesses for the device performing them.

Claim 9

The distribution logic of Claim 1 or 2 wherein said means to control said first and second means to terminate series of accesses is user programmable.