EP0227427A2
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EP
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Method of and circuit for generating bit-order modified binary signals
Assignee: Texas Instruments Inc
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Filing: 1986-12-17
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Granted: —
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Expires: 2006-12-17
Abstract
Abstract A method of and a circuit for generating address signals, wherein a binary index signal and a binary base address signal are stored in index and address registers, respectively, whereupon the index signal and the base address signal are added together to produce an initial output address signal representative of the arithmetic sum of the index and base address signals during an initial cycle of signal generating operation. The initial output address signal is tentatively storing in the address register and is added to the index signal to produce an output address signal differing in bit pattern from the initial output address signal during the cycle of signal generating operation immediately subsequent to the initial cycle. This output signal is likewise tentatively storing in the signal register and thereafter the index signal from the index register and the output address signal produced during each of the successive cycles of signal generating operation are added together to produce another output address signal differing in bit pattern from each of the output address signals produced during the immediately preceding cycle of signal generating operation, wherein the arithmetic sum is produced by carrying out a forward arithmetic addition from the least significant bits forward or a reverse arithmetic addition from the most significant bits backward.
Inventors
- 👤 Shigeshi Abiko
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 15:40
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5055; G06F17/00; G06F17/10; G06F17/14; G06F17/141; G06F17/142; G06F7/501; G06F7/503; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3852
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
227 words
A method of generating binary signals comprising, a) storing in first memory means a binary index signal consisting of a sequence of a predetermined number of bits, b) storing in second memory means a binary base signal consisting of a sequence of said predetermined number of bits, c) adding together said index signal and said base signal for producing an initial output signal representative of the arithmetic sum of the index and base signals during an initial cycle of signal generating operation, d) tentatively storing said initial output signal in said second memory means and adding the initial output signal to said index signal for producing an output signal differing in bit pattern from said initial output signal during the cycle of signal generating operation immediately subsequent to said initial cycle and tentatively storing the last named output signal in said second memory means, and e) thereafter adding together said index signal from said first memory means and the output signal produced during each of the successive cycles of signal generating operation for producing another output signal differing in bit pattern from each of the output signals produced during the immediately preceding cycle of signal generating operation, f) said arithmetic sum being produced by carrying out a forward arithmetic addition from the least significant bits forward or a reverse arithmetic addition from the most significant bits backward.
Claim 2
Independent Claim
227 words
A method of generating binary signals comprising, a) storing in first memory means a binary index signal consisting of a sequence of a predetermined number of bits, b) storing in second memory means a binary base signal consisting of a sequence of said predetermined number of bits, c) adding together said index signal and said base signal for producing an initial output signal representative of the arithmetic sum of the index and base signals during an initial cycle of signal generating operation, d) tentatively storing said initial output signal in said second memory means and adding the initial output signal to said index signal for producing an output signal differing in bit pattern from said initial output signal during the cycle of signal generating operation immediately subsequent to said initial cycle and tentatively storing the last named output signal in said second memory means, and e) thereafter adding together said index signal from said first memory means and the output signal produced during each of the successive cycles of signal generating operation for producing another output signal differing in bit pattern from each of the output signals produced during the immediately preceding cycle of signal generating operation, f) said arithmetic sum being produced by carrying out a forward arithmetic addition from the least significant bits forward or a reverse arithmetic addition from the most significant bits backward.
Claim 3
Independent Claim
237 words
A method of sequentially generating binary address signals comprising, a) storing in an index register a binary index signal consisting of a sequence of a predetermined number of bits, b) storing in an address register a binary base address signal consisting of a sequence of said predetermined number of bits, c) adding together said index signal and said base address signal for producing an initial output address signal representative of the arithmetic sum of the index and base address signals during an initial cycle of signal generating operation, d) tentatively storing said initial output address signal in said address register and adding the initial output address signal to said index signal for producing an output address signal differing in bit pattern from said initial output address signal during the cycle of signal generating operation immediately subsequent to said initial cycle and tentatively storing the last named output signal in said signal register, and e) thereafter adding together said index signal from said index register and the output address signal produced during each of the successive cycles of signal generating operation for producing another output address signal differing in bit pattern from each of the output address signals produced during the immediately preceding cycle of signal generating operation, f) said arithmetic sum being produced by carrying out a forward arithmetic addition from the least significant bits forward or a reverse arithmetic addition from the most significant bits backward.
Claim 4
Independent Claim
237 words
A method of sequentially generating binary address signals comprising, a) storing in an index register a binary index signal consisting of a sequence of a predetermined number of bits, b) storing in an address register a binary base address signal consisting of a sequence of said predetermined number of bits, c) adding together said index signal and said base address signal for producing an initial output address signal representative of the arithmetic sum of the index and base address signals during an initial cycle of signal generating operation, d) tentatively storing said initial output address signal in said address register and adding the initial output address signal to said index signal for producing an output address signal differing in bit pattern from said initial output address signal during the cycle of signal generating operation immediately subsequent to said initial cycle and tentatively storing the last named output signal in said signal register, and e) thereafter adding together said index signal from said index register and the output address signal produced during each of the successive cycles of signal generating operation for producing another output address signal differing in bit pattern from each of the output address signals produced during the immediately preceding cycle of signal generating operation, f) said arithmetic sum being produced by carrying out a forward arithmetic addition from the least significant bits forward or a reverse arithmetic addition from the most significant bits backward.
Claim 5
Dependent Claim
222 words
A bit-order modifiable signal generator circuit, comprising a) an adder circuit comprising the combination of a binary multi-stage adder/subtractor and a forward-reverse selective carry propagation network, the multi-stage adder/subtractor having functions to carry out both a forward arithmetic addition from the least significant bits forward and a reverse arithmetic addition from the most significant bits backward selectively under the control of said forward/reverse selective carry propagation network, b) an index register operable for having programmably yet fixedly stored therein a binary index signal consisting of a sequence of a predetermined number of bits, and c) a signal register operable for having programmably yet fixedly stored therein a binary base signal consisting of a sequence of said predetermined number of bits, d) said adder circuit being responsive to the index signal output from said index register and to a binary signal output from said signal register for producing an output signal representative of the arithmetic sum of the index signal and the signal output from the signal register during each cycle of signal generating operation, e) said signal register being responsive to said output signal from said adder circuit for tentatively storing the output signal from the adder circuit and feeding back the signal to said adder circuit for being arithmetically added to said index signal during each cycle of signal generating operation.
Claim 6
Dependent Claim
222 words
A bit-order modifiable signal generator circuit, comprising a) an adder circuit comprising the combination of a binary multi-stage adder/subtractor and a forward-reverse selective carry propagation network, the multi-stage adder/subtractor having functions to carry out both a forward arithmetic addition from the least significant bits forward and a reverse arithmetic addition from the most significant bits backward selectively under the control of said forward/reverse selective carry propagation network, b) an index register operable for having programmably yet fixedly stored therein a binary index signal consisting of a sequence of a predetermined number of bits, and c) a signal register operable for having programmably yet fixedly stored therein a binary base signal consisting of a sequence of said predetermined number of bits, d) said adder circuit being responsive to the index signal output from said index register and to a binary signal output from said signal register for producing an output signal representative of the arithmetic sum of the index signal and the signal output from the signal register during each cycle of signal generating operation, e) said signal register being responsive to said output signal from said adder circuit for tentatively storing the output signal from the adder circuit and feeding back the signal to said adder circuit for being arithmetically added to said index signal during each cycle of signal generating operation.
Claim 7
Dependent Claim
275 words
A bit-order modifiable address generator circuit having functions to perform a fast Fourier transform algorithm with a predetermined number of sample points set therein, comprising a) an adder circuit comprising the combination of a binary multi-stage adder/subtractor and a forward-reverse selective carry propagation network, the multi-stage adder/subtractor having functions to carry out both a forward arithmetic addition from the least significant bits forward and a reverse arithmetic addition from the most significant bits backward selectively under the control of said forward/reverse selective carry propagation network, b) an index register operable for having programmably yet fixedly stored therein a binary index address signal consisting of a sequence of a predetermined number of bits, the predetermined number of bits being uniquely determined depending upon said predetermined number of sample points set in said fast Fourier transform algorithm, and c) an address register operable for having programmably yet fixedly stored therein a binary base address signal consisting of a sequence of said first predetermined number of bits, d) said adder circuit being responsive to the index address signal output from said index register and to a binary address signal output from said address register for producing an output address signal representative of the arithmetic sum of the index address signal and the address signal output from the address register during each cycle of address generating operation, e) said address register being responsive to said output address signal from said adder circuit for tentatively storing the output address signal from the adder circuit and feeding back the address signal to said adder circuit for being arithmetically added to said index address signal during each cycle of address generating operation.
Claim 8
Dependent Claim
275 words
A bit-order modifiable address generator circuit having functions to perform a fast Fourier transform algorithm with a predetermined number of sample points set therein, comprising a) an adder circuit comprising the combination of a binary multi-stage adder/subtractor and a forward-reverse selective carry propagation network, the multi-stage adder/subtractor having functions to carry out both a forward arithmetic addition from the least significant bits forward and a reverse arithmetic addition from the most significant bits backward selectively under the control of said forward/reverse selective carry propagation network, b) an index register operable for having programmably yet fixedly stored therein a binary index address signal consisting of a sequence of a predetermined number of bits, the predetermined number of bits being uniquely determined depending upon said predetermined number of sample points set in said fast Fourier transform algorithm, and c) an address register operable for having programmably yet fixedly stored therein a binary base address signal consisting of a sequence of said first predetermined number of bits, d) said adder circuit being responsive to the index address signal output from said index register and to a binary address signal output from said address register for producing an output address signal representative of the arithmetic sum of the index address signal and the address signal output from the address register during each cycle of address generating operation, e) said address register being responsive to said output address signal from said adder circuit for tentatively storing the output address signal from the adder circuit and feeding back the address signal to said adder circuit for being arithmetically added to said index address signal during each cycle of address generating operation.
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