Programmable logic device

Claim 2

In a logic device having programmable array means for generating a plurality of data signals and a plurality of dynamic control signals, and having a plurality of input/output ports, a circuit for configuring said input/output ports, comprising: a plurality of programmable output cell means, responsive to a first of said dynamic control signals, each receiving a predetermined one of said data signals, for storing said data signal, for selectively configuring a predetermined one of said input/output ports, and for generating a signal at said input/output port ; and a plurality of storage cell means, responsive to said first dynamic control signal, each receiving a predetermined one of said data signals, for storing said data signal and for generating a signal therefrom; whereby upon reception of a first, respectively, a second, predetermined level of said first dynamic control signal, said output cell means configures said predetermined input/output port to selectively generate said data signal stored or received thereby, said data signal stored in a predetermined one of said storage cell means, respectively.

Claim 3

In a logic device according to claim 1 wherein said programmable output cell means comprises: register means, responsive to a clock signal, receiving said data signal, for registering said data signal and for generating therefrom a registerd signal; output polarity select means responsive to a second of said dynamic control signals, responsive to said registered signal for selectively generating an output signal in an active HIGH mode or an active LOW mode, in response to said second dynamic control signal; output enable control means responsive to a third of said dynamic cotrol signals, receiving a fourth of said dynamic control signals, for selectively generating therefrom an output enable signal and an output disable signal, in response to said third dynamic control signal; and input/output means receiving said output signal, responsive to said first dynamic control signal received at a true input and said output enable and disable signals, for selectively generating therefrom said output signal or said signal generated by said storage cell means at said input/output port, and for receiving a signal received at said input/output port.

Claim 4

In a logic device according to claim 2 wherein said plurality of programmable output cell means comprises a plurality of first and second programmable output cell means, said second output cell means further selectively configuring said input/output port to generate said data signal or said registered signal at said port, said second output cell means further including: output select multiplexer means, responsive to a fifth of said dynamic control signals, receiving said data signal and said registered signal for selectively coupling one of said received signals to said output polarity select means, in response to said fifth dynamic control signal.

Claim 5

In a logic device according to claim 3, said second output cell means further selectively configuring said input/output port to generate said signal received at said port or said registered signal to said programmable array means, said second output cell means further including: feedback multiplexer means, responsive to a sixth of said dynamic control signals, receiving said registered signal and said signal received at said port for selectively coupling one of said received signals to said programmable array means, in response to said sixth dynamic control signal.

Claim 6

In a logic device according to claim 2, said first output cell means further including means for conducting said signal received at said port to said programmable array means.

Claim 7

In a logic device according to claim 1 wherein said plurality of storage cell means comprise: register means responsive to a clock signal, receiving said data signal, for storing said data signal and for generating therefrom said stored data signal; and input/output means receiving said stored data signal, responsive to said first dynamic control signal received at a true input, for selectively conducting said stored data signal to said predetermined input/output port.

Claim 8

In a logic device according to claim 6, said storage cell means further including means for conducting said stored data signal to said programmble array means.

Claim 9

In a logic device according to claim 2, further including a plurality of programmable fusible links, wherein the source of predetermined ones of said dynamic control signals is a predetermined one of said programmable fusible links, the status of which determines said dynamic control signal.

Claim 10

In a logic device according to claim 8 wherein said output enable control means is an exclusive OR gate receiving at a first input terminal said third dynamic control signal and at a second input terminal said fourth dynamic control signal, said fourth dynamic control signal determined by a first of said plurality of programmable fusible links.

Claim 11

In a logic device according to claim 1 wherein said programmable output cell means comprises: register means, responsive to a clock signal, receiving said data signal, for registering said data signal and for generating therefrom a registerd signal; output enable control means responsive to a second of said dynamic control signals, receiving a fourth of said dynamic control signals, for selectively generating therefrom an output enable signal and an output disable signal, in responso to said second dynamic control signal; and input/output means receiving said output signal, responsive to said first dynamic control signal received at a true input and said output enable and disable signals, for selectively generating therefrom said output signal or said signal generated by said storage cell means at said input/output port, and for receiving a signal received at said input/output port.

Claim 12

In a logic device according to claim 10 wherein said plurality of programmable output cell means comprises a plurality of first and second programmable output cell means, said second output cell means further selectively configuring said input/output port to generate said (first) data signal or a second data signal at said port, said second output cell means further including: output select multiplexer means, responsive to a third and a fourth of said dynamic control signals, receiving said second data signal and said registered signal for selectively coupling one of said received signals to said input/output means, in response to said third and fourth dynamic control signals.

Claim 13

12 In a logic device according to claim 11, said second output cell means further selectively configuring said input/output port to generate said signal received at said port or said registered signal to said programmable array means, said second output cell means further including: feedback multiplexer means, responsive to a fifth of said dynamic control signals, receiving said registered signal and said signal received at said port for selectively coupling one of said received signals to said programmable array means, in response to said fifth dynamic control signal.

Claim 14

In a logic device according to claim 11, said second output cell means further including observability means responsive to said first dynamic control signal and a fifth of said dynamic control signals for selectively generating said third dynamic control signal received by said output select multiplexer means.

Claim 15

In a logic device accding to claim 10, further including a plurality of programmable fusible links, wherein the source of predetermined ones of said dynamic control signals is a predetermined one of said programmable fusible links, the status of which determines said dynamic control signal.

Claim 16

In a logic device according to claim 14 wherein said output enable control means is an exclusive OR gate receiving at a first input terminal said second dynamic control signal and at a second input terminal said third dynamic control signal, said third dynamic control signal determined by a first of said plurality of programmable fusible links.

Claim 17

In a logic device according to claims 2, 6 or 10,whereinsaid register means is further responsive to a seventh of said dynamic control signals for asynchronous resetting of said registered signal generated thereby to a predetermined level, in response to said seventh dynamic control signal.

Claim 18

In a logic device according to claims 2, 6 or 10, wherein said register means is further responsive to an eighth of said dynamic control signals for synchronous presetting of said registered signal generated thereby to a predetermined level, in response to said eighth dynamic control signal, upon reception of said clock signal.

Claim 19

In a logic device according to claim 10, wherein said register means is further responsive to a ninth of said dynamic control signals for asynchronous preloading of said register means.

Claim 20

In a programmable logic array device contained on an integrated circuit chip having a portion comprising a plurality of programmable logic cell means dynamically generating logic signals, and a second plurality of first and second programmable combinatorial logic means for combining a subset of logic signals and for generating a plurality of combinatorial signals therefrom, a first and a second plurality of programmable output cells, each cell of said first, said second, plurality responsive to a first, a second, clock signal, respectively, a data signal, being a predetermined one of said first, and said second, combinatorial signals, respectively, and a plurality of dynamic control signals, selectable from signals applied to an external pin of said integrated circuit chip and predetermined ones of said plurality of combinatorial signals generated by said portion of said integrated circuit for configuring a first, a second, plurality, respectively, of input/output ports of said integrated circuit, and a first and a second plurality of storage cells, each cell of said first, said second, plurality responsive to said first, said second, clock signal, respectively, a data signal, being a predetermined one of said first, and second, combinatorial signals, respectively, and a plurality of dynamic control signals, selectable from signals applied to an external pin of said integrated circuit chip and predetermined ones of said plurality of combinatorial signals generated by said portion of said integrated circuit for storing a third, a fourth, plurality, respectively, of said data signals and for generating a third, a fourth, plurality, respectively of signals therefrom, whereby upon reception of a first, respectively, a second, predetermined level of a first of said dynamic control signals, said first, second, plurality, respectively, of output cells configure a predetermined port to generate said data signal stored or received thereby, said data signal stored in a predetermined one of said first, second, plurality, respectively, storage cell means.

Claim 21

In a programmable logic array device contained on an integrated circuit chip having a portion comprising a plurality of programmable logic cell means dynamically generating logic signals, and a second plurality of first and second programmable combinatorial logic means for combining a subset of logic signals and for generating a plurality of combinatorial signals therefrom, a first and a second plurality of programmable output cells, each cell of said first, said second, plurality responsive to a first, a second, clock signal, respectively, a data signal, being a predetermined one of said first, and said second, combinatorial signals, respectively, and a plurality of dynamic control signals, selectable from signals applied to an external pin of said integrated circuit chip and predetermined ones of said plurality of combinatorial signals generated by said portion of said integrated circuit for configuring a first, a second, plurality, respectively, of input/output ports of said integrated circuit, and a first and a second plurality of storage cells, each cell of said first, said second, plurality responsive to said first, said second, clock signal, respectively, a data signal, being a predetermined one of said first, and second, combinatorial signals, respectively, and a plurality of dynamic control signals, selectable from signals applied to an external pin of said integrated circuit chip and predetermined ones of said plurality of combinatorial signals generated by said portion of said integrated circuit for storing a third, a fourth, plurality, respectively, of said data signals and for generating a third, a fourth, plurality, respectively of signals therefrom, whereby upon reception of a first, respectively, a second, predetermined level of a first of said dynamic control signals, said first, second, plurality, respectively, of output cells configure a predetermined port to generate said data signal stored or received thereby, said data signal stored in a predetermined one of said first, second, plurality, respectively, storage cell means.

Claim 22

2 Q A programmable logic array device according to claim 23 wherein said device receives a first and a second bank clock signal, said portion of said plurality of logic cell means receiving said second bank clock signal as its clock signal, said device further including: bank clock select multiplexer means, having a programmable fusible link, receiving said first and said second bank clock signals for selectively coupling one of said received signals to an output of said bank clock select multiplexer means in response to the status of said bank clock select multiplexer fusible link, said signal so-coupled being said clock signals received by said first, said second plurality of output cells, respectively, and by said first and said second plurality of storage cells.

Claim 23

A programmable logic array device according to claim 19 wherein said signals generated by said output cells and said storage cells are fedback to said programmable logic cell means.

Claim 24

A programmable logic array device according to claim 19 wherein said programmable logic cell means is a programmable AND array.

Claim 25

A programmable logic array device according to claim 19 wherein said first and second programmable combinatorial logic means are programmable OR arrays.

Claim 26

In a programmable logic array device contained on an integrated circuit chip having a portion comprising a plurality of programmable logic cell means dynamically generating logic signals, and a second plurality of first and second programmable combinatorial logic means for combining a subset of logic signals and for generating a plurality of combinatorial signals therefrom, a first plurality of programmable output cells, each responsive to a clock signal, a data signal, being a predetermined one of said first combinatorial signals, and a plurality of dynamic control signals, selectable from signals applied to an external pin of said integrated circuit chip and predetermined ones of said plurality of combinatorial signals generated by said portion of said integrated circuit for configuring a plurality, of input/output ports of said integrated circuit, and a plurality of storage cells, each cell responsive to said clock signal, a data signal, being a predetermined one of said second combinalorial signals, and a plurality of dynamic control signals, selectable from signals applied to an external pin of said integrated circuit chip and predetermined ones of said plurality of combinatorial signals generated by said portion of said integrated circuit for storing a plurality of said data signals and for generating a plurality of signals therefrom, whereby upon reception of a first, respectively, a second, predetermined level of a first of said dynamic control signals, said output cells configure a predetermined port to generate said data signal stored or received thereby, said data signal stored in a predetermined one of said storage cell means.

Claim 27

In a programmable logic array device contained on an integrated circuit chip having a portion comprising a plurality of programmable logic cell means dynamically generating logic signals, and a second plurality of first and second programmable combinatorial logic means for combining a subset of logic signals and for generating a plurality of combinatorial signals therefrom, a first plurality of programmable output cells, each responsive to a clock signal, a data signal, being a predetermined one of said first combinatorial signals, and a plurality of dynamic control signals, selectable from signals applied to an external pin of said integrated circuit chip and predetermined ones of said plurality of combinatorial signals generated by said portion of said integrated circuit for configuring a plurality, of input/output ports of said integrated circuit, and a plurality of storage cells, each cell responsive to said clock signal, a data signal, being a predetermined one of said second combinalorial signals, and a plurality of dynamic control signals, selectable from signals applied to an external pin of said integrated circuit chip and predetermined ones of said plurality of combinatorial signals generated by said portion of said integrated circuit for storing a plurality of said data signals and for generating a plurality of signals therefrom, whereby upon reception of a first, respectively, a second, predetermined level of a first of said dynamic control signals, said output cells configure a predetermined port to generate said data signal stored or received thereby, said data signal stored in a predetermined one of said storage cell means.

Claim 30

An n-state machina design method according to claim 25 wherein the contents of said buried registers are observable in a multiplexed manner,at predetermined ones of said output pins, further including the design verification step of: d) observing at said output pins the contents of said i general registers and said j buried registers.