EP0225442A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Equalized biased array for proms and eproms
Assignee: Texas Instruments Inc
•
Filing: 1986-09-17
•
Granted: —
•
Expires: 2006-09-17
Abstract
Abstract An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage V BIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage V T above V BIAS . Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage V T above V BIAS . The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be substantially non-conducting.
Inventors
- 👤 Jeffrey K. Kaszubinski
- 👤 David D. Wilmoth
- 👤 Timmie M. Coffman
- 👤 John F. Schreck
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 08:49
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; G11C16/00; G11C16/02; G11C16/06; G11C16/24
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
124 words
A biasing network for an array of semiconductor memory transistors having associated bit and source lines, comprising: a bias line; biasing means coupled to said bias line for biasing the latter to a preselected voltage; bit means coupled between said bias line and said bit lines for transmitting the voltage on said bias line to said bit lines during a read cycle in response to a control signal V cc ; and source means coupled between said bias line and source lines for transmitting the voltage on said bias line to non-selected source lines in response to a control signal VG; wherein the voltage on said bias line is more than 1 volt less than the voltage of control signals V cc and VG.
Claim 2
Dependent Claim
124 words
A biasing network for an array of semiconductor memory transistors having associated bit and source lines, comprising: a bias line; biasing means coupled to said bias line for biasing the latter to a preselected voltage; bit means coupled between said bias line and said bit lines for transmitting the voltage on said bias line to said bit lines during a read cycle in response to a control signal V cc ; and source means coupled between said bias line and source lines for transmitting the voltage on said bias line to non-selected source lines in response to a control signal VG; wherein the voltage on said bias line is more than 1 volt less than the voltage of control signals V cc and VG.
Claim 3
Dependent Claim
39 words
A biasing network according to claim 1, wherein said bit means is a bit transistor whose source-to-drain path is coupled between said bias line and an associated bit line and whose gate is coupled to a V cc line.
Claim 4
Dependent Claim
37 words
A biasing network according to claim 2, wherein said source means is a source transistor whose source-to-drain path is coupled between said bias line and an associated source line and whose gate is coupled to a line.
Claim 5
Dependent Claim
39 words
A biasing network according to claim 3, wherein said biasing means is a supply transistor whose source-to-drain path is coupled between the V cc line and said bias line and whose gate is coupled to a reference voltage REF.
Claim 6
Dependent Claim
41 words
A biasing network according to claim 4, wherein said bias line is coupled to ground through a bleed transistor whose gate is coupled to the V cc line and whose channel size is much smaller than that of said supply transistor.
Claim 7
Dependent Claim
40 words
A biasing network according to claim 5, wherein the voltages V cc , VG, Y and Z all about equal d.c. voltages greater than 3 volts and the voltage REF is in the range of 2 to V cc volts.
Claim 8
Independent Claim
48 words
A method of biasing an array of semiconductor memory transistors of a type having respective bit and source lines, comprising: establishing a bias voltage; and transmitting said bias voltage onto said bit lines and onto said source lines of non-selected ones of said memory transistors during read modes.
Claim 9
Independent Claim
48 words
A method of biasing an array of semiconductor memory transistors of a type having respective bit and source lines, comprising: establishing a bias voltage; and transmitting said bias voltage onto said bit lines and onto said source lines of non-selected ones of said memory transistors during read modes.
Claim 10
Dependent Claim
69 words
A method according to claim 7, wherein said bias voltage is transmitted to said bit lines by a plurality of transistors each having a source-to-drain path connected between said bias line and an associated bit line and a gate coupled to a V cc line and such that the voltage on said bias line is more than about 1 V T less than that on the V cc line.
Claim 11
Dependent Claim
70 words
A method according to claim 8, wherein said bias voltage is transmitted to said source lines by a plurality of transistors each having a source-to-drain path connected between said bias line and an associated source line and whose gate is coupled to a VG line such that for non-selected transistors, the voltage on the VG line is more than about 1 V T greater than that on said bias line.
Claim 12
Dependent Claim
47 words
A method according to claim 9, wherein said bias voltage is established by coupling the source-to-drain path of a bias transistor between the V cc line and said bias line and its gate to a reference voltage REF whose voltage is below that of V cc .
Claim 13
Dependent Claim
41 words
A method according to claim 10, wherein a bleed path for charge from said bias line is provided by connecting a conducting transistor between said bias line and ground whose channel size is much smaller than that of said bias transistor.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.