EP0225426A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A method of fabricating a MOS transistor on a substrate
Assignee: Thorn EMI North America Inc
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Filing: 1982-12-10
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Granted: —
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Expires: 2002-12-10
Abstract
Abstract The invention relates to fabrication techniques for the construction of MOS transistors to provide source/drain regions (20,22) which are self-aligned and non-overlapping with respect to their gate electrode (16). The non-overlapping feature is provided by defining a gate electrode (16) over a substrate (10), forming an implant mask of dielectric (18), for example, on the sides of the gate electrode (16), and implanting a source/drain region (20,22) such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode (16) and the implanted regions (20,22). The source/drain region (20,22) is then heat driven until its side edge is substantially aligned with the edge of the gate electrode (16). Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and interconnects.
Inventors
- 👤 William D. Ryden
- 👤 Matthew V. Hanson
- 👤 Gary F. Derbenwick
- 👤 Alfred P. Gnadinger
- 👤 James R. Adams
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 19:59
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/60; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10P30/208; H10P30/21; H10P30/212; H10P76/00; H10P76/40; H10P76/408; H10P76/4085
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
220 words
A method of fabricating on a substrate an MOS transistor having a gate electrode and a self-aligned source/drain region with zero overlap, the method comprising the steps of: a) forming a doped polysilicon gate electrode (16) upon but insulated from the substrate (10), b) then differentially thermally growing an oxide (18) to a controlled thickness on the top and sides of the gate electrode (16) and over the substrate (10) adjacent the gate electrode, the oxide on the top and sides of the gate electrode being relatively thick compared to the oxide over an intended source/drain region of the substrate, c) then anisotropically etching said oxide (18) such that said oxide defines an implant mask of controlled width on the sides of the gate electrode (16), d) implanting at least one source/drain region (20,22) in the substrate (10) such that the implant mask (18) shields an underlying portion of the substrate (10) from implantation to provide a gap betwen a side edge of the gate electrode and a side edge of the implanted region, and e) then heat driving the implanted source/drain region (20,22) until its side edge is substantially aligned with the previously separated side edge of the gate electrode (16), whereby the source/drain edge is substantially aligned with the gate electrode edge and there is substantially zero overlap.
Claim 2
Independent Claim
220 words
A method of fabricating on a substrate an MOS transistor having a gate electrode and a self-aligned source/drain region with zero overlap, the method comprising the steps of: a) forming a doped polysilicon gate electrode (16) upon but insulated from the substrate (10), b) then differentially thermally growing an oxide (18) to a controlled thickness on the top and sides of the gate electrode (16) and over the substrate (10) adjacent the gate electrode, the oxide on the top and sides of the gate electrode being relatively thick compared to the oxide over an intended source/drain region of the substrate, c) then anisotropically etching said oxide (18) such that said oxide defines an implant mask of controlled width on the sides of the gate electrode (16), d) implanting at least one source/drain region (20,22) in the substrate (10) such that the implant mask (18) shields an underlying portion of the substrate (10) from implantation to provide a gap betwen a side edge of the gate electrode and a side edge of the implanted region, and e) then heat driving the implanted source/drain region (20,22) until its side edge is substantially aligned with the previously separated side edge of the gate electrode (16), whereby the source/drain edge is substantially aligned with the gate electrode edge and there is substantially zero overlap.
Claim 3
Dependent Claim
20 words
A method as claimed in Claim 1, wherein the oxide is grown in steam at a temperature of about 850°C.
Claim 4
Dependent Claim
25 words
A method as claimed in Claim 1 or 2, wherein the source/drain region (20,22) is implanted through the relatively thin oxide layer over the substrate.
Claim 5
Dependent Claim
39 words
A method as claimed in Claim 1 or 2, wherein said step of anisotropically etching removes the oxide (18) over the intended source/drain region (20,22) and yet leaves masking oxide (B) on the sides of the gate electrode (16).
Claim 6
Independent Claim
135 words
A method as claimed in any preceding claim, further comprising, after said implanting step, forming an intermediate dielectric (24) over both the gate electrode (16) and the source/drain region (20,22), patterning a contract area over the source/drain region (20,22) to overlie the source/drain region and overlap the oxide on the gate electrode (16), etching dielectric (24) in the contact area down to the substrate (10) while leaving the oxide (18) on the sides and top of the gate electrode (16), and providing a conductive material (32,34) in the etched contact area to provide a contact for the source/drain region (20,22), whereby a self-aligned contact is formed such that the gate electrode (16) is prohibited by the oxide (18) over the gate electrode from being shorted in the event that the patterned contact area is misaligned.
Claim 7
Independent Claim
34 words
A method as claimed in any preceding claim, wherein said substrate is monocrystalline silicon, and said gate electrode (16) is doped to a value arranged to promote a high rate of differential thermal oxidation.
Claim 8
Independent Claim
26 words
A method as claimed in any preceding claim, wherein said gate electrode (16) is polysilicon doped to a sheet resistance of about 20 ohms per square.
Claim 9
Independent Claim
56 words
A method as claimed in any preceding claim, wherein the oxide is anisotropically etched to leave oxide on at least the sides of said gate electrode (16b), and the source/drain region (20b,22b) is implanted while the top of the gate electrode (16b) is substantially free of oxide for doping the gate electrode (16b) during source/drain implantation.
Claim 10
Dependent Claim
40 words
A method as claimed in Claim 8, wherein a relatively thin oxide (48) is formed over the gate electrode (16b), the oxide remnants (46a,46b) on the sides of the gate electrode, and the intended source/drain region (20a,22b) prior to implantation.
Claim 11
Independent Claim
145 words
A method of fabricating on a substrate an MOS transistor having a gate electrode and at least one source/drain region, comprising forming a gate electrode (16) insulated from the substrate (10), forming an implant mask (18) of a controlled width on the sides of the gate electrode (16), implanting at least one source/drain region (20,22) in the substrate (10) such that the implant mask (18) shields an underlying portion of the substrate (10) from implantation to provide a gap between a side edge of the gate electrode (16) and a side edge of the implanted region (20,22), and heat driving the implanted source/drain region until its side edge is substantially aligned with the previously separated side edge of the gate electrode (16) such that no substantial gap or overlap exists between the source/drain region and the gate electrode, wherein said implant mask comprises photoresist remnants.
Claim 12
Independent Claim
145 words
A method of fabricating on a substrate an MOS transistor having a gate electrode and at least one source/drain region, comprising forming a gate electrode (16) insulated from the substrate (10), forming an implant mask (18) of a controlled width on the sides of the gate electrode (16), implanting at least one source/drain region (20,22) in the substrate (10) such that the implant mask (18) shields an underlying portion of the substrate (10) from implantation to provide a gap between a side edge of the gate electrode (16) and a side edge of the implanted region (20,22), and heat driving the implanted source/drain region until its side edge is substantially aligned with the previously separated side edge of the gate electrode (16) such that no substantial gap or overlap exists between the source/drain region and the gate electrode, wherein said implant mask comprises photoresist remnants.
Claim 13
Dependent Claim
97 words
A method as claimed in Claim 10, wherein said photoresist remanants are established by placing a conforming layer of photoresist (50) over the gate electrode (16c) and over the intended source/drain region (20c,22c) such that a greater depth (I) of photoresist occurs adjacent the edges of the gate electrode (16c) than over the top of the gate electrode and over other areas of the intended source/drain region, and removing photoresist from the top of the gate electrode and from the source/drain region so as to leave photoresist remnants (50a,50b) on the sides of the gate electrode (16c).
Claim 14
Dependent Claim
33 words
A method as claimed in Claim 11, including forming an oxide layer over the gate electrode prior to the application of the photoresist to prevent doping of the gate electrode during source/drain implant.
Claim 15
Independent Claim
226 words
A method of fabricating on a substrate an MOS transistor having a gate electrode and a pair of source/drain regions, comprising forming a relatively thin gate insulator (14) over the substrate (10) and over the intended source/drain regions (20,22) defining a polysilicon gate electrode (16) over the gate insulator (14) between the intended source/drain regions (20,22), establishing a dielectric layer (18) over the gate electrode (16) and the gate insulator (14) such that the dielectric (18) is relatively thick at least over the sides of the gate electrode (16) and relatively thinner over the intended source/drain regions (20,22), implanting the source/drain regions (20,22) such that they are laterally offset from the substrate area below the gate electrode (16) by the thickness of the dielectric layer (18) on the sides of the gate electrode (16), heat driving the source/drain regions (20,22) laterally until their edges are substantially vertically aligned with the sides of the gate electrode (16), etching contact areas so as to lay bare the substrate (10) holding the source/drain regions (20,22) and yet maintaining the dielectric (18) on the sides of the gate electrode (16), and forming conductive contacts (32,24) in the etched areas, whereby the source/drain regions (20,22) are properly aligned with the gate electrode (16) and the metal contacts (32,34) are aligned with the source/drain regions (20,22) without shorting the gate electrode (16).
Claim 16
Independent Claim
226 words
A method of fabricating on a substrate an MOS transistor having a gate electrode and a pair of source/drain regions, comprising forming a relatively thin gate insulator (14) over the substrate (10) and over the intended source/drain regions (20,22) defining a polysilicon gate electrode (16) over the gate insulator (14) between the intended source/drain regions (20,22), establishing a dielectric layer (18) over the gate electrode (16) and the gate insulator (14) such that the dielectric (18) is relatively thick at least over the sides of the gate electrode (16) and relatively thinner over the intended source/drain regions (20,22), implanting the source/drain regions (20,22) such that they are laterally offset from the substrate area below the gate electrode (16) by the thickness of the dielectric layer (18) on the sides of the gate electrode (16), heat driving the source/drain regions (20,22) laterally until their edges are substantially vertically aligned with the sides of the gate electrode (16), etching contact areas so as to lay bare the substrate (10) holding the source/drain regions (20,22) and yet maintaining the dielectric (18) on the sides of the gate electrode (16), and forming conductive contacts (32,24) in the etched areas, whereby the source/drain regions (20,22) are properly aligned with the gate electrode (16) and the metal contacts (32,34) are aligned with the source/drain regions (20,22) without shorting the gate electrode (16).
References Cited (Backward Citations)
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