Lateral insulated gate transistor with improved latch up immunity

Claim 2

A lateral insulated gate transistor having a substantially planar upper surface comprising: a substrate of one type conductivity; a first layer of one type conductivity; a second layer of said opposite type conductivity forming a portion of said surface of said device; a first region of said opposite type conductivity disposed within said second layer and forming a portion of said surface of said device; a second region of said one type conductivity disposed in said first region forming a portion of said surface; a third region of said one type conductivity disposed within said second layer and forming a portion of said surface; of said surface; a fourth region of said opposite type conductivity disposed in said third region forming a portion of said surface; an insulation layer disposed on the surface of said device covering a portion of said third and fourth regions; a controllable gate electrode covering a portion of the insulation layer in registry with said third and fourth regions responsive to an appropriate bias for inducing a channel in said third region coupling said second layer to said fourth region; said channel when induced having sufficient capacity for conducting a substantial portion of the lateral device current; an electrode disposed over and in contact with a portion of said third and fourth regions, shorting said third region to said second region to inhibit inadvertent forward biasing said junction between said third and fourth regions; and means associated with said third region controlling flow of carriers of said one type conductivity in said third region.

Claim 3

The lateral insulated gate transistor of claim 1 wherein said means associated with said third region includes in said second layer a high conductivity path of said one type conductivity spaced away from the junctino between said third and fourth regions.

Claim 4

The lateral insulated gate transistor of claim 1 wherein said means associated with said third region includes in said third region a high conductivity channel of said one type conductivity.

Claim 5

The lateral insulated gate transistor of claim 1 wherein said means associated with said third region controlling flow of carriers of said one type conductivity in said third region comprises a further region of said one type conductivity overlapping said third region and increasing the conductivity of a portion said third region.

Claim 6

The lateral insulated gate transistor of claim 1 wherein said means associated with said third region is adjacent said third region.

Claim 7

The lateral insulated gate transistor of claim 1 wherein said means associated with said third region in major portion is adjacent and underlies a portion of said third region directly beneath said electrode and offset from said fourth region.

Claim 8

The lateral insulated gate transistor of claim 1 wherein said means associated with said third region established a highly conductive minority carrier path between said electrode and said second layer.

Claim 9

The lateral insulated gate transistor of claim 7 wherein said highly conductive minority carrier current path is transverse to the plane of said surface of said device.

Claim 10

The lateral insulated gate transistor of claim 1 wherein said means associated with said third region comprises a further region of said one type conductivity disposed in said first and second layers forming a high conductivity lateral channel for lateral movement of said one type carriers beneath said second region.

Claim 11

The lateral insulated gate transistor of claim 9 wherein said third region includes a path of said one conductivity type, a first portion of which is substantially parallel to the plane of said surface of said device and second portion of which is transverse to the plane of said surface of said device, said first portion having a resistivity Rl; and said further region established lateral Path having a resistivity R2 wherein R2 is less than R1.

Claim 12

The lateral insulated gate transistor of claim 4 wherein said further region is disposed in said second layer and underlies and is coextensive with said second region.

Claim 13

The lateral insulated gate transistor of claim 4 wherein said further region is heavily doped.

Claim 14

The lateral insulated gate transistor of claim 4 wherein said further region is formed by diffusion.

Claim 15

The lateral insulated gate transistor of claim 6 wherein said further region is a buried layer.

Claim 16

The lateral insulated gate transistor of claim 6 wherein said third region is disposed in said further region.

Claim 17

The lateral insulated gate transistor of claim 1 wherein said first and second layers are epitaxial layers.

Claim 18

The lateral insulated gate transistor of claim 1 wherein said substrate is heavily doped and provides vertical current flow between said substrate and said anode.

Claim 19

The lateral insulated gate transistor of claim 1 wherein said first layer is a lightly doped epitaxial layer.

Claim 20

The lateral insulated gate transistor of claim 1 wherein said second layer is lightly doped.

Claim 21

2C. The lateral insulated gate transistor of claim 1 wherein said first region is heavily doped.

Claim 22

The lateral insulated gate transistor of claim 1 wherein said second region is lightly doped.

Claim 23

The lateral insulated gate transistor of claim 1 wherein said third regin is heavily doped.

Claim 24

A lateral insulated gate transistor with improved latching immunity comprising: a first layer of one type conductivity; a second layer of said opposite type conductivity forming a portion of a said surface of transistor; a first region of said opposite type conductivity disposed within said second layer and forming a portion of said surface of said device; a second region of one type conductivity disposed within said first region forming a portion of said surface of said device; a third region of said one type conductivity disposed within said first layer and forming a portion of said surface; a fourth region of said opposite type conductivity disposed in said third region and forming a portion of said surface; an insulation layer disposed on the surface of the transistor covering a portion of said third and fourth regions; a controllable gate electrode covering a portion of said insulation layer in registry with said regions responsive to an appropriate bias for inducing a channel in said third region coupling said second layer to said fourth region; said channel when induced having sufficient capacity for conducting a substantial portion of the majority carrier lateral current of said device; an electrode disposed over and in contact with a portion of said third and fourth regions shorting said third region to said fourth region to inhibit forward biasing said junction between said third and fourth regions; and means associated with said third region forming a high conductivity channel for controlling the flow of carriers of said one type conductivity in said third region.

Claim 25

A lateral insulated gate transistor with improved latching immunity comprising: a first layer of one type conductivity; a second layer of said opposite type conductivity forming a portion of a said surface of transistor; a first region of said opposite type conductivity disposed within said second layer and forming a portion of said surface of said device; a second region of one type conductivity disposed within said first region forming a portion of said surface of said device; a third region of said one type conductivity disposed within said first layer and forming a portion of said surface; a fourth region of said opposite type conductivity disposed in said third region and forming a portion of said surface; an insulation layer disposed on the surface of the transistor covering a portion of said third and fourth regions; a controllable gate electrode covering a portion of said insulation layer in registry with said regions responsive to an appropriate bias for inducing a channel in said third region coupling said second layer to said fourth region; said channel when induced having sufficient capacity for conducting a substantial portion of the majority carrier lateral current of said device; an electrode disposed over and in contact with a portion of said third and fourth regions shorting said third region to said fourth region to inhibit forward biasing said junction between said third and fourth regions; and means associated with said third region forming a high conductivity channel for controlling the flow of carriers of said one type conductivity in said third region.

Claim 26

A lateral insulated gate transistor with improved current flow and latching immunity comprising: a heavily doped substrate of one type conductivity; a first lightly doped layer of one type conductivity; a second lightly doped layer of said opposite -type conductivity-forming a portion of said surface of the device; first region of said opposite type conductivity disposed within said second layer a portion forming a portion of said surface of said device; a second region cf heavily doped region of said one type conductivity disposed within said first region and forming a portion of said surface of said device; a third lightly doped region of said one type conductivity disposed within said first layer and forming a portion of said surface; a fourth heavily doped region of said opposite type conductivity disposed in said second region and forming a portion of said surface; an insulation layer disposed on said surface of the device covering a portion of said third and fourth regions; a controllable gate electrode covering a portion of the insulation layer in registry with said third and fourth regions responsive to an appropriate bias for inducing a channel in said third region; said channel when induced having a sufficient capacity for conducting a substantial portion of the majority carrier current of said device between said second layer and said fourth region; an electrode disposed over and in electrical contact with a portion of said third and fourth regions -shorting said third region to said fourth region to inhibit forward biasing of said function between said third and fourth regions.

Claim 27

A lateral insulated gate transistor with improved current flow and latching immunity comprising: a heavily doped substrate of one type conductivity; a first lightly doped layer of one type conductivity; a second lightly doped layer of said opposite -type conductivity-forming a portion of said surface of the device; first region of said opposite type conductivity disposed within said second layer a portion forming a portion of said surface of said device; a second region cf heavily doped region of said one type conductivity disposed within said first region and forming a portion of said surface of said device; a third lightly doped region of said one type conductivity disposed within said first layer and forming a portion of said surface; a fourth heavily doped region of said opposite type conductivity disposed in said second region and forming a portion of said surface; an insulation layer disposed on said surface of the device covering a portion of said third and fourth regions; a controllable gate electrode covering a portion of the insulation layer in registry with said third and fourth regions responsive to an appropriate bias for inducing a channel in said third region; said channel when induced having a sufficient capacity for conducting a substantial portion of the majority carrier current of said device between said second layer and said fourth region; an electrode disposed over and in electrical contact with a portion of said third and fourth regions -shorting said third region to said fourth region to inhibit forward biasing of said function between said third and fourth regions.

Claim 28

25 : A method for forming an insulated gate transistor exhibiting improved current conductivity and improved latching having substantially planar surface comprising the steps of: providing a heavily doped substrate layer of said one type conductivity; establishing a heavily doped buried region of said one type conductivity in said substrate layer; forming a first lightly doped layer of said one conductivity on said substrate; forming a second lightly doped layer of said opposite type conductivity on said first layer; establishing a first region of said opposite type conductivity in said second lightly.doped layer, said first region forming'a portion of said substantially planar surface; establishing a second region of said one type conductivity in said first region, said second region forming a portion of said substantially planar surface; establishing a third region of said one type conductivity in said second lightly doped layer in substantial registry with said buried region, said third region forming a portion of said substantially planar surface; establishing a fourth region of said opposite type conductivity in said third region, said fourth region forming a portion of said substantially planar surface and defining a channel portion of said third region between fourth region and said first layer proximate said surface; establishing a metallized electrode in registry with and in electrical contact with a portion of said third and fourth regions for inhibiting the forward biasing of the junction between said third and fourth regions; establishing an insulation layer over said channel portion; and establishing a gate metallization over said insulation layer for inducing a conductive channel in said channel portion; and causing said heavily doped region to diffuse from said substrate into said first and second lightly doped layers to establish in said second layer a diffused portion and a highly conductive path beneath and substantially laterally coextensive with said second region for diverting carriers into said conductive path in said diffused portion of said buried region.

Claim 29

25 : A method for forming an insulated gate transistor exhibiting improved current conductivity and improved latching having substantially planar surface comprising the steps of: providing a heavily doped substrate layer of said one type conductivity; establishing a heavily doped buried region of said one type conductivity in said substrate layer; forming a first lightly doped layer of said one conductivity on said substrate; forming a second lightly doped layer of said opposite type conductivity on said first layer; establishing a first region of said opposite type conductivity in said second lightly.doped layer, said first region forming'a portion of said substantially planar surface; establishing a second region of said one type conductivity in said first region, said second region forming a portion of said substantially planar surface; establishing a third region of said one type conductivity in said second lightly doped layer in substantial registry with said buried region, said third region forming a portion of said substantially planar surface; establishing a fourth region of said opposite type conductivity in said third region, said fourth region forming a portion of said substantially planar surface and defining a channel portion of said third region between fourth region and said first layer proximate said surface; establishing a metallized electrode in registry with and in electrical contact with a portion of said third and fourth regions for inhibiting the forward biasing of the junction between said third and fourth regions; establishing an insulation layer over said channel portion; and establishing a gate metallization over said insulation layer for inducing a conductive channel in said channel portion; and causing said heavily doped region to diffuse from said substrate into said first and second lightly doped layers to establish in said second layer a diffused portion and a highly conductive path beneath and substantially laterally coextensive with said second region for diverting carriers into said conductive path in said diffused portion of said buried region.

Claim 30

The method of forming an insulated gate transistor with improved latching immunity of claim 25 further comprising the steps of: forming said conductive path substantially parallel to the surface of said device.

Claim 33

The method of forming an insulated gate transistor with improved latching immunity of claim 27 wherein said base region is established with a conductivity of in excess of 10 18 Carriers/cc.

Claim 34

The method of forming an insulated gate transistor with improved latching immunity of claim 27 further comprising the steps of: forming said conductive path substantially parallel to said surface of said device.

Claim 37

The method of forming an insulated gate transistor with improved latching immunity of claim 30 further comprising the steps of: providing a heavily doped substrate layer of said one type conductivity beneath said first layer for increasing the current conductivity of said device.

Claim 38

The method of forming an insulated gate transistor with improved latching immunity of claim 30 further comprising the steps of: fourth region is formed overlapping said heavily doped region.