EP0221741A2
Expired / Lapsed
EP
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Computer microsequencers
Assignee: Advanced Micro Devices Inc
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Filing: 1986-10-24
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Granted: —
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Expires: 2006-10-24
Abstract
Abstract A microsequencer suitable for use in real time data processing computer applications is described. The microsequencer permits the utilization of a wide variety of program execution control structures, such as multiply-nested iterative looping, subroutine calls, branching multiple-interrupt servicing, all in a manner that is both instruction code and execution speed efficient. This is a accomplished by providing a microsequencer for producing execution point addresses in the execution of a program including nested program segments of one or more program instructions, the microsequencer comprising sequencer means for generating successive execution point addresses, the sequencer means including branch control means for providing a branch address to the sequencer means as a generated execution point address, the branch control means being responsive to a condition input, and nest control means, responsive to the sequencer means, for detecting changes in the effective segment nest level of the execution point address and for providing a corresponding condition input to the branch control means.
Inventors
- 👤 Bu Chin Wang
- 👤 Dakshesh Parikh
- 👤 Marita Daly
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 16:50
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/322; G06F9/325; G06F9/22; G06F9/26; G06F9/262
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
98 words
Apparatus for providing execution point addresses in the execution of a program including nested program segments of one or more program instructions, said apparatus comprising: a) sequencer means for generating successive execution point addresses, said sequencer means including branch control means for providing a branch address to said sequencer means as a generated execution point address and for receiving a condition input; and b) nest control means, responsive to said sequencer means, for detecting changes in the effective segment nest level of the execution point address and for providing a corresponding condition input to said branch control means.
Claim 2
Dependent Claim
98 words
Apparatus for providing execution point addresses in the execution of a program including nested program segments of one or more program instructions, said apparatus comprising: a) sequencer means for generating successive execution point addresses, said sequencer means including branch control means for providing a branch address to said sequencer means as a generated execution point address and for receiving a condition input; and b) nest control means, responsive to said sequencer means, for detecting changes in the effective segment nest level of the execution point address and for providing a corresponding condition input to said branch control means.
Claim 3
Dependent Claim
49 words
The apparatus of Claim 1 further comprising: a) first stack means, responsive to said sequencer control means, for storing branch instruction address pointers; and b) second stack means, responsive to said nest control means, for storing data corresponding to the effective segment nest level of the execution point address.
Claim 4
Dependent Claim
24 words
The apparatus of Claim 2 wherein said nest control means comprises means for determining the absolute segment nest level of said execution point address.
Claim 5
Dependent Claim
18 words
The apparatus of Claim 3 wherein said branch control means comprises loop means for performing end-of-loop instructionless loops.
Claim 6
Dependent Claim
102 words
Apparatus for providing execution point addresses in the execution of a program including nested program segments of one or more program instructions, said apparatus comprising: a) sequencer means for generating successive execution point addresses, said sequencer means including branch control means for providing a branch address to said sequencer means as a generated execution point address, said branch control means being responsive to a condition input; and b) nest control means, responsive to said sequencer means, for detecting changes in the effective segment nest level of the execution point address and for providing a corresponding condition input to said branch control means.
Claim 7
Dependent Claim
102 words
Apparatus for providing execution point addresses in the execution of a program including nested program segments of one or more program instructions, said apparatus comprising: a) sequencer means for generating successive execution point addresses, said sequencer means including branch control means for providing a branch address to said sequencer means as a generated execution point address, said branch control means being responsive to a condition input; and b) nest control means, responsive to said sequencer means, for detecting changes in the effective segment nest level of the execution point address and for providing a corresponding condition input to said branch control means.
Claim 8
Dependent Claim
55 words
The apparatus of Claim 5 wherein said branch control means comprises: a) means for storing a loop ending address pointer; b) means for storing a loop iteration value; and c) means for comparing said loop iteration value with a predetermined value and for effectively comparing said loop ending address pointer with the execution point address.
Claim 9
Dependent Claim
56 words
The apparatus of Claim 6 wherein said branch control means further comprises loop stack means for retrievably storing loop ending address pointers and corresponding loop iteration values, said branch control means storing and retrieving loop ending pointers and corresponding loop iteration values in response to segment nest level changes as detected by said nest control means.
Claim 10
Dependent Claim
23 words
The apparatus of Claim 7 wherein said nest control means further comprises nest stack means for retrievably storing segment nest level corresponding values.
Claim 11
Dependent Claim
73 words
Apparatus for controlling the execution point address of a program having instructions provided at corresponding addresses and grouped into a plurality of program segments, said apparatus comprising: a) sequencing means for altering the execution point address of said program; b) means for storing a nested segment count value; and c) means, responsive to said sequencing means, for adjusting said nested segment value on program segment nest level changes of the execution point address.
Claim 12
Dependent Claim
73 words
Apparatus for controlling the execution point address of a program having instructions provided at corresponding addresses and grouped into a plurality of program segments, said apparatus comprising: a) sequencing means for altering the execution point address of said program; b) means for storing a nested segment count value; and c) means, responsive to said sequencing means, for adjusting said nested segment value on program segment nest level changes of the execution point address.
Claim 13
Dependent Claim
83 words
The apparatus of Claim 9 further comprising: a) first stack means for retrievably storing a plurality of execution point address pointers; b) second stack means for retrievably storing a plurality of nested segment count values; and c) means for the ordered storage and retrieval of said an execution point address pointer and said nested segment count value to or from said first stack means and said second stack means, respectively, in response to the execution of an instruction at the execution point address.
Claim 14
Dependent Claim
58 words
The apparatus of Claim 10 wherein aid sequencing means comprises: a) means for storing a pointer to a segment ending address; b) means for storing a segment iteration count value; and c) means for effectively comparing the execution point address with said segment ending address pointer and for comparing said stored iteration count value with a predetermined value.
Claim 15
Dependent Claim
80 words
The apparatus of Claim 11 further comprising: a) second stack means for retrievably storing a plurality of segment ending address pointers; b) third stack means for retrievably storing a plurality of segment interation count values; and c) means for the ordered storage and retrieval of said an execution point address pointer and said nested segment count value to or from said second stack means and said third stack means, respectively, in response to an instruction at the execution point address.
Claim 16
Dependent Claim
63 words
The controller of Claim 9 wherein said sequencing means comprises: a) first means for determining the completion of a nest segment; b) second means for comparing the number of iterations of said nest segment with a predetermined number; and c) means, responsive to said first and second means, for altering the execution point address to the corresponding beginning address of said nest segment.
Claim 17
Dependent Claim
47 words
The controller of Claim 13 wherein said first means comprises: a) means for storing an address pointer to the last program instruction of a corresponding nest segment; and b) means for comparing the execution point address that referenced by the address pointer stored by said storing means.
Claim 18
Dependent Claim
62 words
Apparatus for programmable processing of control and data signals in accordance with a predetermined sequence of instructions, said apparatus comprising: a) means for storing a plurality of program instructions at a corresponding plurality of program addresses; b) means for selectively fetching program instructions; and c) an instruction address sequencer unit including means for the over-head free nestable loop sequencing of instruction addresses.
Claim 19
Dependent Claim
62 words
Apparatus for programmable processing of control and data signals in accordance with a predetermined sequence of instructions, said apparatus comprising: a) means for storing a plurality of program instructions at a corresponding plurality of program addresses; b) means for selectively fetching program instructions; and c) an instruction address sequencer unit including means for the over-head free nestable loop sequencing of instruction addresses.
Claim 20
Dependent Claim
73 words
The apparatus of Claim 15 wherein said nestable loop sequencing means comprises: a) means for storing a first pointer to a predetermined initial instruction of a loop sequence of said instructions; b) means for storing a second pointer to a predetermined terminal instruction of said loop sequence of said instructions; and c) means for iteratively modifying an iteration count value corresponding to the cumulative loop performance of said loop sequence of said instructions.
Claim 21
Dependent Claim
42 words
The controller of Claim 16 further comprising: a) first means for buffering a plurality of said first pointers; b) second means for buffering a plurality of said second pointers; and c) third means for buffering a plurality of said iteration count values.
Claim 22
Dependent Claim
19 words
The controller of Claim 17 wherein said first, second and third buffering means are further characterized as LIFO buffers.
Claim 23
Dependent Claim
23 words
The controller of Claim 18 wherein said pointer of said second means is further characterized as being relative to said predetermined initial instruction.
References Cited (Backward Citations)
No citation records indexed.
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