EP0221574B1 — Circuit arrangement for a pulse-controlled ac reg…

Claim 1

Independent Claim 359 words

Circuit arrangement comprising an alternating current load (3), which is connectable to an alternating voltage source (1, 2) and has an inductive component, comprising a controlled load-current switching means (8, 23) arranged electrically in series to the alternating-voltage load (3), comprising a control network (75, 18) for controlling the load-current switching means (8, 23) via a pulse frequency located substantially above the alternating-voltage frequency, the pulse-frequency or the mark-space ratio of the control pulses being adjustable via a regulating unit (S) in such a way that the alternating-current load (3) is supplied with an alternating current clocked by the pulse frequency, and comprising two antiparallel freewheeling arms, which are located parallel to the alternating-current load (3) and are alternately controllable by means of freewheeling switching means (4, 5; 6, 7) depending upon the alternating-current supply voltage zero-axis crossing, it being the case that, during the positive half-wave of the alternating current supply voltage, the freewheeling arm with the freewheeling switching means (4, 5) blocks and the freewheeling arm with the freewheeling switching means (6, 7) conducts, and that, during the negative half-wave of the alternating-current supply voltage, the freewheeling arm with the freewheeling switching means (4, 5) conducts in the freewheeling arm with the freewheeling switching means (6, 7) blocks, characterized in that a holding circuit (13, 15) is provided, which either directly or indirectly influences the load-current switching means (8, 23) via the control network (75,18) in such a way that, during a hold range (H) located in the region of the zero-axis crossing of the alternating voltage, the load current switching means (8, 23) remains either in an opened or in a closed switch position, it being the case that a first hold-range limit (H i ) limiting the hold range (H) is temporally predetermined at the latest by the zero-axis crossing of the alternating voltage, and a second hold-range limit (H 2 ) is temporally predetermined at the earliest by the following zero-axis crossing of the lagging alternating current, and that the hold range (H) covers at least that phase range 0 < φ x < 4 > 1 in which disturbing induced voltage pulses occur.

Claim 2

Dependent Claim 359 words

Circuit arrangement comprising an alternating current load (3), which is connectable to an alternating voltage source (1, 2) and has an inductive component, comprising a controlled load-current switching means (8, 23) arranged electrically in series to the alternating-voltage load (3), comprising a control network (75, 18) for controlling the load-current switching means (8, 23) via a pulse frequency located substantially above the alternating-voltage frequency, the pulse-frequency or the mark-space ratio of the control pulses being adjustable via a regulating unit (S) in such a way that the alternating-current load (3) is supplied with an alternating current clocked by the pulse frequency, and comprising two antiparallel freewheeling arms, which are located parallel to the alternating-current load (3) and are alternately controllable by means of freewheeling switching means (4, 5; 6, 7) depending upon the alternating-current supply voltage zero-axis crossing, it being the case that, during the positive half-wave of the alternating current supply voltage, the freewheeling arm with the freewheeling switching means (4, 5) blocks and the freewheeling arm with the freewheeling switching means (6, 7) conducts, and that, during the negative half-wave of the alternating-current supply voltage, the freewheeling arm with the freewheeling switching means (4, 5) conducts in the freewheeling arm with the freewheeling switching means (6, 7) blocks, characterized in that a holding circuit (13, 15) is provided, which either directly or indirectly influences the load-current switching means (8, 23) via the control network (75,18) in such a way that, during a hold range (H) located in the region of the zero-axis crossing of the alternating voltage, the load current switching means (8, 23) remains either in an opened or in a closed switch position, it being the case that a first hold-range limit (H i ) limiting the hold range (H) is temporally predetermined at the latest by the zero-axis crossing of the alternating voltage, and a second hold-range limit (H 2 ) is temporally predetermined at the earliest by the following zero-axis crossing of the lagging alternating current, and that the hold range (H) covers at least that phase range 0 < φ x < 4 > 1 in which disturbing induced voltage pulses occur.

Claim 3

Dependent Claim 58 words

Circuit arrangement according to Claim 1, characterized in that the load-current switching means (8, 23) has an uncontrolled bridge rectifier (23), which is located with its alternating-voltage terminals in series with the alternating-current load (3), and a controlled semiconductor switch (8), preferably a transistor, which with its break section by-passes the direct-voltage arm of the bridge rectifier (23).

Claim 4

Dependent Claim 93 words

Circuit arrangement according to one of the preceding claims, characterized in that the holding circuit (13, 15) has a voltage detector (13) and a first pulse generator (15), in that the input signal fed to the voltage detector (13) is derived directly or indirectly from the alternating voltage of the alternating-voltage source, and in that the output signal transmitted by the voltage detector (13) triggers the input of the first pulse generator (15), the output thereof being connected to the control network (75, 18) of the semiconductor switch (8), possibly via inserted components.

Claim 5

Dependent Claim 58 words

Circuit arrangement according to Claim 3, characterized in that the input signal fed to the voltage detector (13) is tapped by one of the direct-current terminals of the bridge rectifier (23) and routed via an integrator (11), which suppresses the pulse frequency, so that only the envelope curve of the signal coming from the bridge recitifer (23) remains.

Claim 6

Dependent Claim 60 words

Circuit arrangement according to one of Claims 3 to 4, characterized in that at each triggering the first pulse generator (15) forms a holding pulse of specific pulse width, the pulse width corresponding to the maximum hold range (H), and the control pulses coming from the control network (75, 18) being ineffective for as long as the holding pulse lasts.

Claim 7

Dependent Claim 48 words

Circuit arrangement according to one of the preceding claims, characterized in that the holding pulse fed to the semiconductor switch (8) either acts upon the control network (75, 18) and prevents the latter from transmitting a pulsating control signal, or blanks out the pulsating control signal by superposition.

Claim 8

Dependent Claim 52 words

Circuit arrangement according to one of the preceding claims, characterized in that the first hold range limit (H,) defining the start of the hold range (H) is located temporally so far before the alternating voltage zero-axis crossing that the Du/ dt-sensitive components are not damaged or impermissibly influenced by inductive voltage peaks.

Claim 9

Dependent Claim 101 words

Circuit arrangement according to one of the preceding claims, characterized in that the second hold range limit (H 2 ) defining the end of the hold range (H) is fixed in accordance with the cos φ in the load-current circuit in such a way that for cos 0 = 1 the second hold-range limit (H 2 ) falls at the earliest in the zero-axis crossing of the voltage, and as cos (p becomes smaller is displaced in a lagging fashion with the zero-axis crossing of the current so far that it comes to be located therein or immediately before or after.

Claim 10

Dependent Claim 119 words

Circuit arrangement according to Claim 8, characterized in that a control circuit ensures automatic matching of the second hold-range limit (H2) to the respective cos O due to the fact that a third precision resistor (34) is located as current sensor in series with the break section of the semiconductor switch (8), and in that the voltage drop occurring at it is the input quantity of a current detector (46), which in the case of I(t) = 0 or I(t) = 0 delivers a reset pulse to a second pulse generator (16), triggered by the voltage detector (13), precisely when the voltage detector (13), after passing through a monotonically falling voltage level, has detected U(t) = 0 immediately before.

Claim 11

Dependent Claim 363 words

Circuit arrangement according to Claims 5 and 9, characterized in that the potential of a terminal of the direct-current arm of the bridge rectifier (23) is routed via a diode (51) poled in the conducting direction to the parallel connection of a capacitor (55) to a series connection formed by a resistor (52), a Zener diode (53) and a resistor (54), in that the voltage potential present between the Zener diode (53) and the resistor (54) is applied to the inverting input and the reference voltage signal set between the voltage divider resistors (58, 59) is applied to the non-inverting input of a first comparator (56), in that via the output of the first comparator (56), which output is connected via the resistor (60) to the non-inverting input, there are triggered in parallel both a first monostable multivibrator (61, 62, 63), which is formed from the series connection of a capacitor (61) to a diode (62) that is poled in the reverse direction and by-passed by a resistor (63), and a second monostable multivibrator (64, 65, 66), which is formed from the series connection of a capacitor (64) to a diode (65) that is poled in the reverse direction and by-passed by a resistor (66), in that the potentials tapped immediately behind the capacitors (61, 64) are conducted, via diodes (67, 68) poled in the conducting direction in each case, to the input of a NAND gate connected as an inverter (70), which input is connected via a resistor (69) to a first potential tap (57), in that the output of the inverter (70) is applied to a first input of a NAND gate (71) of a pulse generator (18) and regulating potentiometer (75) network (71 to 76), and in that a first terminal of the regulating potentiometer (75) is applied via the series connection of a diode (73), poled in the conducting direction, with a resistor (72), and in common with a second terminal of the regulating potentiometer (75), routed via a diode (74) poled in the reverse direction, to a second input of the NAND gate (71), the latter being connected via a coupling capacitor (76) to the first potential tap

Claim 12

Dependent Claim 283 words

(57), in that the output of the NAND gate (71) triggers both the setting contact of the regulating potentiometer (75) and the gate electrode (37) of the semiconductor switch (8), in that the input signal, detected at the second potential tap (90), for the current detector (46) is fed via an input resistor (77) to the non-inverting input of a second comparator (82) and coupled via a capacitor (80) to the first potential tap (57), in that the output of the second comparator (82) is capacitively coupled with its non-inverting input via a capacitor (81) and is connected immediately behind the capacitor (83) to the inverting input of a third comparator (88) via a third monostable multivibrator (83, 84, 85) formed from the series connection of a capacitor (83) with a diode (85) that is poled in the reverse direction and by-passed by a resistor (84), it being the case that the reference voltage signal required for the inverting input of the second comparator (82) is tapped between the series-connected voltage divider resistors (78, 79), and the reference voltage signal required for the non-inverting input of the third comparator (88) is tapped between the series-connected voltage divider resistors (86, 87), and that the voltage divider network (78, 79, 86, 87) is supplied on the input side via a supply potential (91), and is fed back on the output side to the first potential tap (57), and in that the trigger signal that is present at the output of the third comparator (88) and is transmitted via a diode (89) poled in the reverse direction triggers the first monostable multivibrator (61, 62, 63) between the capacitor (61) and the anode of the diode (68).

Claim 13

Dependent Claim 283 words

(57), in that the output of the NAND gate (71) triggers both the setting contact of the regulating potentiometer (75) and the gate electrode (37) of the semiconductor switch (8), in that the input signal, detected at the second potential tap (90), for the current detector (46) is fed via an input resistor (77) to the non-inverting input of a second comparator (82) and coupled via a capacitor (80) to the first potential tap (57), in that the output of the second comparator (82) is capacitively coupled with its non-inverting input via a capacitor (81) and is connected immediately behind the capacitor (83) to the inverting input of a third comparator (88) via a third monostable multivibrator (83, 84, 85) formed from the series connection of a capacitor (83) with a diode (85) that is poled in the reverse direction and by-passed by a resistor (84), it being the case that the reference voltage signal required for the inverting input of the second comparator (82) is tapped between the series-connected voltage divider resistors (78, 79), and the reference voltage signal required for the non-inverting input of the third comparator (88) is tapped between the series-connected voltage divider resistors (86, 87), and that the voltage divider network (78, 79, 86, 87) is supplied on the input side via a supply potential (91), and is fed back on the output side to the first potential tap (57), and in that the trigger signal that is present at the output of the third comparator (88) and is transmitted via a diode (89) poled in the reverse direction triggers the first monostable multivibrator (61, 62, 63) between the capacitor (61) and the anode of the diode (68).

Claim 14

Dependent Claim 86 words

Circuit arrangement according to one of the preceding claims, characterized in that there is located as freewheeling switch (4,6) in each of the antiparallel connected freewheeling arms a thyristor or a triac of which the break section is by-passed in parallel via the series connection of an RC element (27, 26; 29, 28), and a diode (5, 7), which is poled antiparallel in relation to the diode (5, 7) located in the respective other freewheeling arm, is located in series with this circuit in each case.

Claim 15

Dependent Claim 70 words

Circuit arrangement according to one of the preceding claims, characterized in that triacs serve as freewheeling switches (4, 6) of which the gate electrodes are connected via RD elements (24, 25; 30, 31) in each case to the same alternating-voltage supply terminal (2) of the alternating-voltage source, the trigger diodes (25, 31) connecting the two gate electrodes of the triacs to voltage in opposition only during a specific half-wave period.

Claim 16

Dependent Claim 176 words

Circuit arrangement according to Claim 12, characterized in that additional, pulsating triac (4, 6) trigger networks (T,,T 2 , R,,R Z ,R 4 ; T 3 ,T 4 , R 5 ,R 6 ,R 7 ,R 8 , D 3 ) that guarantee triac triggering are inserted in each case between the gate electrodes of the triacs, which serve as freewheeling switches (4, 6), and the RD elements (24, 25; 30, 31) and in that an additional supply circuit (ZD,, D 2 , C" R 3 ) is provided for said trigger networks in such a way that there is arranged between the alternating-voltage supply terminals (1,2) a series connection of a coupling capacitor (C,), by-passed by a Zener diode (ZD,), of a resistor (R 3 ), and of a coupling diode (D 2 ), and in that the cathode of the Zener diode (ZD,) is connected to the potential of the alternating voltage terminal (1), and the cathode of the diode (D 2 ) is connected to the potential of the alternating voltage terminal (2).

Claim 17

Dependent Claim 364 words

Circuit arrangement according to Claim 13, characterized in that the collectors of the NPN transistor (T,) and of the PNP transistor (T 2 ), on the one hand, the emitters of the NPN transistor (T 3 ) and of the PNP transistor (T 4 ), on the other hand, and the emitter of the NPN transistor (T,) and the collector of the PNP transistor (T 4 ) are connected to one another, in that base and emitter of the NPN transistor (T,) are by-passed by means of resistor (R,), base and emitter of the PNP transistor (T 2 ) are by-passed by means of resistor (R 2 ), base and emitter of the NPN transistor (T 3 ) are by-passed by means of resistor (R 6 ), and base and emitter of the PNP transistor (T 4 ) are by-passed by means of resistor (R 7 ), in that the base of the NPN transistor (T,) is connected to the resistor (24) of the RD element (24, 25) and the base of the PNP transistor (T 4 ) is connected to the resistor (30) of the RD element (30, 31), in that the base potential of the PNP transistor (T2) is routed via the associated base resistor (R 4 ) to the anode of the first freewheeling diode (5) and the base potential of the NPN transistor (T 3 ) is routed via the associated base resistor (R 5 ) to the cathode of the second freewheeling diode (7), in that the potential of the alternating-voltage terminal (1) is routed via a diode (D3) poled in the reverse direction to the base of the NPN transistor (T 3 ) and via a resistor (R a ) to the emitters of the transistors (T 3 , T 4 ), and in that the supply potential tapped from the supply circuit (Zdl, C1, R3, D2) between capacitor (C1) and resistor (R3) is routed to the emitter of the transistor (T1) and to the collector of the transistor (T4), and the respective gate electrode of the triacs (4, 6) is triggered by the emitter potential of the transistor (T2) or the collector potential of the transistor (T3).

Claim 18

Dependent Claim 48 words

Circuit arrangement according to one of the preceding claims, characterized in that the pulse frequency transmitted by the pulse generator (18) of the control network (75, 18) is more than twice as high as the nominal frequency of the alternating voltage, but is preferably greater than 16 Khz.

Claim 19

Dependent Claim 184 words

Circuit arrangement according to one of the preceding claims, characterized in that there is provided for the controlled semiconductor switch (8) a protective circuit, located in its control circuit, in the form of a peak current limiting network (I) and of an r.m.s. current limiting network (II), in the case of the latter an actual-value sensor (G) transmitting to a downstream comparator (K 2 ) an actual value which it forms from the load current flowing through the break section of the semiconductor switch (8), the comparator (K 2 ) comparing the actual value with a predeterminable desired value and changing its circuit state on the output side as soon as the load current exceeds the permissible r.m.s. value, and the binary output signal of the comparator (K 2 ) being fed to a time former (Z), which transmits to the control circuit of the semiconductor switch (8) via a switching logic (L11) blocking pulses through which the duration of the blocking phases of the controlled semiconductor switch (8) is increased so far that the load current is reduced to a permissible r.m.s. value.

Claim 20

Dependent Claim 151 words

Circuit arrangement according to Claim 16, characterized in that there is located in series with the break section of the semiconductor switch (8) a first precision resistor (32), of which the voltage drop occurring thereat represents the input quantity both of the peak current limiting network (I) and of the r.m.s. current limiting network (11), or in that a second precision resistor (33) is located in series in addition to the first precision resistor (32), the voltage drop occurring overall along the two precision resistors (32, 33) representing the input quantity of the r.m.s. current limiting network (II), and the voltage drop occurring along the first precision resistor (32) representing the input quantity of the peak current limiting network (I), and the comparator (K 2 ) of the r.m.s. current limiting network (II) responding to a substantially lower voltage level than the comparator (K,) of the peak current limiting network (I).

Claim 21

Dependent Claim 87 words

Circuit arrangement according to one of Claims 16 to 17, characterized in that the actual-value sensor (G), which has an integrator resistor (44) and an integrator capacitor (45) in a low-pass four-poled circuit, transmits an actual value proportional to the arithmetic mean of the load current at its output which is applied to the input of the comparator (K 2 ), and the form faktor of the load current is taken into account via the level of the desired value and the duration of the blocking pulses.

Claim 22

Dependent Claim 105 words

Circuit arrangement according to one of Claims 16 to 18, characterized in that the output of the comparator (K 2 ) is connected in parallel to a timeformer capacitor (42) of the time former (Z), in that the time former capacitor (42) is connected to a supply potential (40) via a time former resistor (41) located in series with it, and in that the second NPN transistor (43) serving as comparator (K 2 ) is driven by means of the actual value present at the output of the actual-value sensor (G) to block or conduct respectively upon undershooting or overshooting of a maximum r.m.s. current.

Claim 23

Dependent Claim 91 words

Circuit arrangement according to one of Claims 16to 19, characterized in that the switching logic (L11) has a first NAND gate (38), of which the first input is connected to a pulse generator (18) and of which the second input is connected to the collector potential of the second NPN transistor (43), and has a second NAND gate (39), which is connected as an inverter at the output of the first NAND gate (38) and of which the output is applied to the gate electrode (37) of the semiconductor switch (8).

Circuit arrangement for a pulse-controlled ac regulator

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