EP0221307A2
Expired / Lapsed
EP
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Signal electrode drive apparatus for use in a liquid crystal display
Assignee: Casio Computer Co Ltd
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Filing: 1986-09-18
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Granted: —
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Expires: 2006-09-18
Abstract
Abstract In the signal electrode drive apparatus for use in a liquid crystal display, the signal electrode drive circuit (3a) for driving a liquid crystal display panel (LCD) is comprised of a latch circuit (2l) for latching a digitized video signal, a buffer (22), a graduation signal-forming circuit (23), an intensity modulation pulse-generating circuit (25), and an analog multiplexer (24). The latch circuit (2l) holds the video data only once during one horizontal scanning period till the next latch pulse M is generated, thus considerably reducing current dissipation.
Inventors
- 👤 Masao Patent Dept. Hamura R&D Center Kawamura
- 👤 Minoru Patent Dept. Hamura R&D Center Usui
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-10 01:32
CPC Classifications
H; H04; H04N; H04N3/00; H04N3/10; H04N3/12; H04N3/127
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
125 words
A signal electrode drive apparatus for use in a liquid crystal display, characterized by comprising: latch circuit means (2l) including m stages of shift registers and m buffer registers (22), one shift register in each stage successively shifting a latch pulse M in synchronism with fundamental clocks, to generate m latch clocks Tl to Tm with different phases, and each of said buffer registers latching in parallel fashion the n-bit video data in synchronism with the latch clocks φTl to φTm output from said shift registers, the buffer registers of each stage being coupled with said video data; and means (23) for generating signal electrode drive signals for a liquid crystal panel, by using the video data latched in the buffer register at each stage.
Claim 2
Dependent Claim
125 words
A signal electrode drive apparatus for use in a liquid crystal display, characterized by comprising: latch circuit means (2l) including m stages of shift registers and m buffer registers (22), one shift register in each stage successively shifting a latch pulse M in synchronism with fundamental clocks, to generate m latch clocks Tl to Tm with different phases, and each of said buffer registers latching in parallel fashion the n-bit video data in synchronism with the latch clocks φTl to φTm output from said shift registers, the buffer registers of each stage being coupled with said video data; and means (23) for generating signal electrode drive signals for a liquid crystal panel, by using the video data latched in the buffer register at each stage.
References Cited (Backward Citations)
No citation records indexed.
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