EP0219831A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method of producing semiconductor integrated circuit device including bipolar transistor and insulated gate field effect transistor
Assignee: NEC Corp
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Filing: 1986-10-17
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Granted: —
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Expires: 2006-10-17
Abstract
Abstract A method of producing an integrated circuit device having a bipolar transistor and P-channel and N-channel MOS transistors (Bi-CMOS IC) is disclosed. This method includes the steps of forming a collector contact hole, depositing a polycrystalline silicon layer after formation of the collector contact hole, and diffusing impurities from the polycrystalline silicon layer into a collector region through the collector contact hole to form a collector contact region. The polycrystalline silicon layer doped with impurities is employed as a collector electrode and gate electrodes. The impurities in the collector contact region are re-diffused into the collector region by the subsequent heat treatments for forming an emitter region and source and drain regions of the respective MOS transistors. An Bi-CMOS IC in which the collector resistance of the bipolar transistor is lowered is thereby produced without great increase in manufacturing steps.
Inventors
- 👤 Katsumoto Soejima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 09:43
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/17; H10P32/171; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10P32/14; H10P32/1408; H10P32/1414; H10W; H10W20/00; H10W20/01; H10W20/021
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
166 words
A method of producing a semiconductor device of a type in which a bipolar transistor and an insulated gate field effect transistor are formed on one chip, said method comprising the steps of forming a collector region of one conductivity type of said bipolar transistor and a substrate region of the opposite conductivity type of said insulated gate field effect transistor in said chip, forming an insulating layer on said collector region and said substrate region, forming a collector contact hole in said insulating layer to selectively expose said collector region, depositing a polycrystalline silicon layer having a portion filling said collector contact hole diffusing impurities for said polycrystalline silicon layer through said collector contact hole into said collector region to form a collector contact region in said collector region, and selectively removing said polycrystalline silicon layer to form on said substrate region a gate electrode of said insulated gate field effect transistor and in said collector contact hole a collector electrode of said bipolar transistor.
Claim 2
Independent Claim
166 words
A method of producing a semiconductor device of a type in which a bipolar transistor and an insulated gate field effect transistor are formed on one chip, said method comprising the steps of forming a collector region of one conductivity type of said bipolar transistor and a substrate region of the opposite conductivity type of said insulated gate field effect transistor in said chip, forming an insulating layer on said collector region and said substrate region, forming a collector contact hole in said insulating layer to selectively expose said collector region, depositing a polycrystalline silicon layer having a portion filling said collector contact hole diffusing impurities for said polycrystalline silicon layer through said collector contact hole into said collector region to form a collector contact region in said collector region, and selectively removing said polycrystalline silicon layer to form on said substrate region a gate electrode of said insulated gate field effect transistor and in said collector contact hole a collector electrode of said bipolar transistor.
Claim 3
Dependent Claim
33 words
The method as claimed in claim 1, further comprising the step of simultaneously forming an emitter region of said bipolar transistor and source and drain regions of said insulated gate field effect transistor.
Claim 4
Independent Claim
152 words
A method of producing a semiconductor device including a bipolar transistor and an insulated gate field effect transistor, comprising the steps of forming a collector region of said bipolar transistor, forming a substrate region of said insulated gate field effect transistor, covering said collector region with an insulating film having a collector contact hole, covering said channel region with a gate insulating film, forming a base region in said collector region, forming a polycrystalline silicon contact doped with a first impurity and making contact with a part of said collector region through said collector contact hole, doping said first impurity from said polycrystalline silicon contact into said collector region to form a collector contact region in said collector region, forming a polycrystalline silicon gate electrode on said gate insulating film, and doping a second impurity into said substrate region to form source and drain regions of said insulated gate field effect transistor.
Claim 5
Independent Claim
152 words
A method of producing a semiconductor device including a bipolar transistor and an insulated gate field effect transistor, comprising the steps of forming a collector region of said bipolar transistor, forming a substrate region of said insulated gate field effect transistor, covering said collector region with an insulating film having a collector contact hole, covering said channel region with a gate insulating film, forming a base region in said collector region, forming a polycrystalline silicon contact doped with a first impurity and making contact with a part of said collector region through said collector contact hole, doping said first impurity from said polycrystalline silicon contact into said collector region to form a collector contact region in said collector region, forming a polycrystalline silicon gate electrode on said gate insulating film, and doping a second impurity into said substrate region to form source and drain regions of said insulated gate field effect transistor.
Claim 6
Dependent Claim
24 words
The method as claimed in claim 3, wherein said first impurities have a diffusion coefficient later than the diffusion coefficient of said second impurities.
Claim 7
Independent Claim
242 words
A method of producing integrated circuit device including a bipolar transistor, a first insulated gate transistor of a first channel type and a second insulated gate transistor of a second channel type on a single wafer, comprising the steps of forming a collector region of said bipolar transistor in said wafer, forming a first substrate region of said first insulated gate transistor in said wafer, forming a second substrate region of said second insulated gate transistor in said wafer, covering said collector region, said first substrate region and said second substrate region with a first insulating film having a collector contact hole, forming a base region in said collector region, depositing a polycrystalline silicon layer making contact with a part of said collector region through said collector contact region and extending over said first insulating film, doping a first impurity into said collector region from said polycrystalline silicon layer through said collector contact hole to form a collector contact region, patterning said polycrystalline silicon layer to form a collector electrode filling said collector contact hole and first and second gate electrodes above said first and second substrate regions, respectively, selectively doping a second impurity into said base region and said first substrate region to form an emitter region and source and drain regions of said first insulated gate transistor, and selectively doping a third impurity into said second substrate region to form source and drain regions of said second insulated gate transistor.
Claim 8
Independent Claim
242 words
A method of producing integrated circuit device including a bipolar transistor, a first insulated gate transistor of a first channel type and a second insulated gate transistor of a second channel type on a single wafer, comprising the steps of forming a collector region of said bipolar transistor in said wafer, forming a first substrate region of said first insulated gate transistor in said wafer, forming a second substrate region of said second insulated gate transistor in said wafer, covering said collector region, said first substrate region and said second substrate region with a first insulating film having a collector contact hole, forming a base region in said collector region, depositing a polycrystalline silicon layer making contact with a part of said collector region through said collector contact region and extending over said first insulating film, doping a first impurity into said collector region from said polycrystalline silicon layer through said collector contact hole to form a collector contact region, patterning said polycrystalline silicon layer to form a collector electrode filling said collector contact hole and first and second gate electrodes above said first and second substrate regions, respectively, selectively doping a second impurity into said base region and said first substrate region to form an emitter region and source and drain regions of said first insulated gate transistor, and selectively doping a third impurity into said second substrate region to form source and drain regions of said second insulated gate transistor.
Claim 9
Dependent Claim
23 words
The method as claimed in claim 5, wherein a diffusion coefficient of said first impurity is larger than that of said second impurity.
Claim 10
Dependent Claim
21 words
The method as claimed in claim 5, wherein said first impurity is phosphorus and said second impurity is arsenic or antimony.
References Cited (Backward Citations)
No citation records indexed.
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