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EP0219291A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

CMOS integrated circuit for signal delay

Assignee: Yamaha Corp
•
Filing: 1986-10-06
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Granted: —
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Expires: 2006-10-06
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Abstract

Abstract A CMOS integrated circuit for signal delay comprises CMOS gate circuits (20) connected in multiple-­stages which deliver out an input binary signal after delaying it by a predetermined delay time. The CMOS gate circuits are arranged in a folded pattern on an integrated circuit substrate and each row of the folded pattern including a part of the CMOS gate circuits in stages of an odd number. Each of the CMOS gate circuits consists of an N channel element (2) and a P channel element (1) cascade-connected to each other and gate patterns of the respective channels have there width and length adjusted in such a manner that value of operating currents in these elements become equal to each other when the same external voltage has been applied to these elements.

Inventors

  • 👤 Norio Tomisawa

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-28 00:16
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H03; H03K; H03K5/00; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/0015; H03K2005/00195; H10D84/83138

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 65 words
A CMOS integrated circuit for signal delay comprising CMOS gate circuits connected in multiple-­stages which deliver out an input binary signal after delaying it by a predetermined delay time, said CMOS gate circuits being arranged in a folded pattern on an integrated circuit substrate and each row of said folded pattern including a part of said CMOS gate circuits in stages of an odd number.
Claim 2
Dependent Claim 65 words
A CMOS integrated circuit for signal delay comprising CMOS gate circuits connected in multiple-­stages which deliver out an input binary signal after delaying it by a predetermined delay time, said CMOS gate circuits being arranged in a folded pattern on an integrated circuit substrate and each row of said folded pattern including a part of said CMOS gate circuits in stages of an odd number.
Claim 3
Dependent Claim 29 words
A CMOS integrated circuit as defined in claim 1 wherein a CMOS gate circuit having a large current supply capacity is provided at the last stage of each row.
Claim 4
Dependent Claim 49 words
A CMOS integrated circuit as defined in claim 2 wherein each row of said folded pattern consists of blocks of an odd number each of which has stages of an odd number and has a CMOS gate circuit having a large current supply capacity at the last stage thereof.
Claim 5
Dependent Claim 21 words
A CMOS integrated circuit as defined in claim 3 wherein said blocks have stages of different odd number from one another.
Claim 6
Dependent Claim 73 words
A CMOS integrated circuit as defined in claim 1 wherein each of said CMOS gate circuits consists of an N channel element and a P channel element cascade-­connected to each other and gate patterns of the respective channel elements have their width and length adjusted in such a manner that values of operating currents in these elements become equal to each other when the same external voltage has been applied to these elements.
Claim 7
Dependent Claim 38 words
A CMOS integrated circuit as defined in claim 5 wherein the ratio of width to length of the gate pattern of the N channel element is smaller than that of the gate pattern of the P channel element.
Claim 8
Dependent Claim 29 words
A CMOS integrated circuit as defined in claim 6 wherein a CMOS gate circuit having a large current supply capacity is provided at the last stage of each row.
Claim 9
Dependent Claim 49 words
A CMOS integrated circuit as defined in claim 7 wherein each row of said folded pattern consists of blocks of an odd number each of which has stages of an odd number and has a CMOS gate circuit having a large current supply capacity at the last stage thereof.
Claim 10
Dependent Claim 21 words
A CMOS integrated circuit as defined in claim 8 wherein said blocks have stages of different odd number from one another.

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