EP0219203A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Computer control providing single-cycle branching
Assignee: Advanced Micro Devices Inc
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Filing: 1986-08-14
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Granted: —
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Expires: 2006-08-14
Abstract
Abstract An instruction processor suitable for use in a reduced instruction-set computer employing an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register. The condition bit and the branch target address determine which instruction is to be fetched, the branch not taking effect until the next-following instruction is executed. In this manner, no replacement of the instruction which physically follows the branch instruction in the pipeline need be made, and the branch occurs within the single cycle of the pipeline allocated to it. A simple circuit implements this delayed-branch method. A computer incorporating the processor readily executes special-handling techniques for calls on subroutines, interrupts and traps.
Inventors
- 👤 Brian Case
- 👤 Rod Fleck
- 👤 Ole Moller
- 👤 Cheng-Gang Kong
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 07:45
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3005; G06F9/30058; G06F9/32; G06F9/322; G06F9/323; G06F9/38; G06F9/3836; G06F9/3842
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
169 words
A digital instruction processor control which cyclically executes, in a single cycle, instructions from a set, including a plurality of plural-bit branch instructions, stored in an instruction cache having a plurality of locations each with a designator, said processor control comprising: means for generating signals indicative of a "continue with next instruction" address: means responsive to said continue address signals and to predetermined bit portions of said branch instructions for generating signals indicative of a "branch target" address; and first multiplexer means having an output terminal connected to said instruction cache responsive to a control signal indicative of the contents of a predetermined "condition" bit portion of said branch instruction, to said branch target address signals applied to a first input terminal thereof and said continue address signals applied to a second input terminal thereof for selectively conducting to said output terminal one of said address signals indicative of a location within said instruction cache from which to fetch the next instruction to be processed by said instruction processor.
Claim 2
Dependent Claim
169 words
A digital instruction processor control which cyclically executes, in a single cycle, instructions from a set, including a plurality of plural-bit branch instructions, stored in an instruction cache having a plurality of locations each with a designator, said processor control comprising: means for generating signals indicative of a "continue with next instruction" address: means responsive to said continue address signals and to predetermined bit portions of said branch instructions for generating signals indicative of a "branch target" address; and first multiplexer means having an output terminal connected to said instruction cache responsive to a control signal indicative of the contents of a predetermined "condition" bit portion of said branch instruction, to said branch target address signals applied to a first input terminal thereof and said continue address signals applied to a second input terminal thereof for selectively conducting to said output terminal one of said address signals indicative of a location within said instruction cache from which to fetch the next instruction to be processed by said instruction processor.
Claim 3
Dependent Claim
192 words
A digital instruction processor control according to claim 1 wherein said branch target address generating means comprises: second multiplexer/register means having an output terminal connected to said first input terminal of said first multiplexer means responsive to a control signal indicative of which of said plurality of branch instructions is being executed, to signals applied to a first input terminal indicative of an "indirect address" determined by said branch instructions, and to signals applied to a second input terminal indicative of a "relative or absolute branch address" for selectively conducting to said output terminal one of said address signals indicative of said branch target address; and adder means having an output terminal connected to said second input terminal of said second multiplexer/register means responsive to said control signal indicative of which of said plurality of branch instructions is being executed, to signals applied to a first input terminal indicative of a predetermined "branch displacement" portion of said branch instructions, and to said continue address signals applied to a second input terminal for selectively generating at said output terminal an arithmetical combination of said signals applied to said first and second input terminals.
Claim 4
Dependent Claim
133 words
A digital instruction processor control according to claim 1 further including means connected to said output terminal of said first multiplexer means for storing at least three signals indicative of instruction cache location designators, each instruction therein designated occupying a stage in an instruction "pipeline", for generating signals representative of said contents stored therein, and for updating the contents of said location designators stored therein so that said instruction cache location designator conducted by said first multiplexer during the preceding cycle of said instruction processor replaces the contents of a first storage location thereof, the instruction cache location designator stored in said first storage location replaces the contents of a second storage location, and the instruction cache location designator stored in said second storage location replaces the contents of a third storage location.
Claim 5
Dependent Claim
73 words
A digital instruction processor according to claim 3 wherein said pipeline means comprises a first clocked register having an input terminal connected to said output terminal of said first multiplexer means and an output terminal, a second clocked register having an input termirial connected to said output terminal of said first register and an output terminal, and a third register having an input terminal connected to said output terminal of said second register.
Claim 6
Independent Claim
174 words
A method of performing branches in one cycle of a digital instruction processor control having a program counter which cyclically executes instructions from a set, including a plurality of branch instructions each determining a "branch condition", stored in an instruction cache having a plurality of locations each with a designator, comprising the steps of: a) fetching from said cache at the location designator specified by the contents of said program counter a branch instruction and storing said instruction in an instruction register; b) decoding said instruction stored in said instruction register; c) saving said branch condition determined by said instruction; d) determining a branch target address based on the information generated at decoding step (c), and the contents of said program counter; e) fetching an instruction from a location in said cache determined from said branch target address determined at step (d), and said branch condition information generated at step (c); and f) replacing the contents of the program counter with the address used to fetch said instruction at step (e) incremented by one.
Claim 7
Independent Claim
174 words
A method of performing branches in one cycle of a digital instruction processor control having a program counter which cyclically executes instructions from a set, including a plurality of branch instructions each determining a "branch condition", stored in an instruction cache having a plurality of locations each with a designator, comprising the steps of: a) fetching from said cache at the location designator specified by the contents of said program counter a branch instruction and storing said instruction in an instruction register; b) decoding said instruction stored in said instruction register; c) saving said branch condition determined by said instruction; d) determining a branch target address based on the information generated at decoding step (c), and the contents of said program counter; e) fetching an instruction from a location in said cache determined from said branch target address determined at step (d), and said branch condition information generated at step (c); and f) replacing the contents of the program counter with the address used to fetch said instruction at step (e) incremented by one.
Claim 8
Dependent Claim
79 words
A one-cycle branching method according to claim 5 further including a method for calling a procedure in one cycle wherein said instruction set further includes a procedure call instruction, wherein step (a) calls for fetching said procedure call instruction, said method further including the steps of: g) determining a call return address based on the information generated at decoding step (b) and the contents of said program counter; and h) saving said call return address determined at step (g).
Claim 9
Independent Claim
142 words
A method of processing an interrupt routine by a digital instruction processor control having an instruction pipeline which cyclically executes instructions from a set stored in an instruction cache having a plurality of locations each with a designator, comprising the steps of: a) saving the location designator of the instruction placed in the pipeline two cycles prior to the occurrence of the interrupt; b) saving the location designator of the instruction placed in the pipeline one cycle prior to the occurrence of the interrupt; c) transferring control to the first instruction of said interrupt routine; d) prior to returning from said interrupt routine fetching for said pipeline the instruction located at the location designator saved at step (a); and e) prior to returning from said interrupt routine fetching for said pipeline the instruction located at the location designator saved at step (b).
Claim 10
Independent Claim
142 words
A method of processing an interrupt routine by a digital instruction processor control having an instruction pipeline which cyclically executes instructions from a set stored in an instruction cache having a plurality of locations each with a designator, comprising the steps of: a) saving the location designator of the instruction placed in the pipeline two cycles prior to the occurrence of the interrupt; b) saving the location designator of the instruction placed in the pipeline one cycle prior to the occurrence of the interrupt; c) transferring control to the first instruction of said interrupt routine; d) prior to returning from said interrupt routine fetching for said pipeline the instruction located at the location designator saved at step (a); and e) prior to returning from said interrupt routine fetching for said pipeline the instruction located at the location designator saved at step (b).
Claim 11
Dependent Claim
164 words
An interrupt processing method according to claim 7 wherein said instruction processor control has a program counter and a data path pipeline, said instruction set includes an interrupt procedure call instruction, and wherein transferring control step (c) comprises the steps of: cl) fetching from said cache at the location designator specified by the contents of said program counter said interrupt procedure call instruction and storing said instruction in an instruction register; c2) decoding said instruction stored in said instruction register; c3) determining a branch target address based on the information generated at decoding step (c2), and the contents of said program counter; c4) fetching an instruction from a location in said cache determined from said branch target address determined at step (c3); c5) replacing the contents of the program counter with the address used to fetch said instruction at step (c4) incremented by four; and c6) conducting the contents of said program counter to said data path pipeline for use in subsequent storage operations.
Claim 12
Dependent Claim
68 words
An interrupt processing method according to claim 7, further including the steps of: f) following return from said interrupt routine fetching from said cache at the location designator saved at step (a) and storing said instruction in an instruction register; and g) following return from said interrupt routine fetching from said cache at the location designator saved at step (b) and storing said instruction in an instruction register.
Claim 13
Dependent Claim
138 words
An interrupt processing method according to claim 9, wherein said instruction processor control has a program counter, said instruction set includes an interrupt procedure call instruction, and wherein fetching step (f) comprises the steps of: fl) fetching from said cache at the location designator specified by the contents of said program counter said indirect branch instruction and storing said instruction in an instruction register; f2) decoding said instruction stored in said instruction register; f3) determining an indirect branch address based on the information generated at decoding step (f2), and the contents of said program counter; f4) fetching an instruction from a location in said cache determined from said indirect branch address determined at step (f3); and c5) replacing the contents of the program counter with the address used to fetch said instruction at step (f4) incremented by one.
References Cited (Backward Citations)
No citation records indexed.
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