EP0218426A2
Expired / Lapsed
EP
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Bus interface
Assignee: Nortel Networks Ltd
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Filing: 1986-09-26
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Granted: —
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Expires: 2006-09-26
Abstract
Abstract A bus interface for interfacing between a processor and a shared bus is disclosed. The bus interface allows the exchange of data in the form of packets between the bus and the processor. An interface control device exchanges control data with the shared bus (e.g. identification signals, polling signals, control signals) in order to regulate accesses of the interface circuit to the shared bus. State machines (e.g. a transmitter and a receiver) including data pipelines, are responsive to control signals from the interface control device for exchanging data between the shared bus and a data storage device. An access control device both controls the flow of data between the processor and the data storage device and regulates access to the data storage device between the processor and the state machines.
Inventors
- 👤 Paul Arthur Devries
- 👤 Brian Ronald Smith
- 👤 Jay Scott Parker
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 07:24
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/128; G06F13/14; G06F13/36; G06F13/362; G06F13/366; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4213
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
144 words
An interface circuit (2O) for interfacing between a shared bus (21) and a processor (22), both for extracting information, in the form of packets, from said bus and for transmitting information, in the form of packets, to said bus, said interface circuit characterized by: interface control means (51, 57) for receiving control information from said shared bus and transmitting control information to said shared bus; receiver means (53), responsive to control signals from said interface control means, for receiving data from said shared bus and for routing said data to a temporary data storage means (26); transmitter means (52), responsive to control signals from said interface control means, for transmitting data from said temporary data storage means to said shared bus; and access control means (42, 43) for controlling the flow of data between said processor (22) and said temporary data storage means (26).
Claim 2
Dependent Claim
144 words
An interface circuit (2O) for interfacing between a shared bus (21) and a processor (22), both for extracting information, in the form of packets, from said bus and for transmitting information, in the form of packets, to said bus, said interface circuit characterized by: interface control means (51, 57) for receiving control information from said shared bus and transmitting control information to said shared bus; receiver means (53), responsive to control signals from said interface control means, for receiving data from said shared bus and for routing said data to a temporary data storage means (26); transmitter means (52), responsive to control signals from said interface control means, for transmitting data from said temporary data storage means to said shared bus; and access control means (42, 43) for controlling the flow of data between said processor (22) and said temporary data storage means (26).
Claim 3
Dependent Claim
46 words
The interface circuit (2O) of claim 1 wherein said access control means (42, 43) and said bus control means (51, 57) interact such that the processor (22) has access to said storage means (26) no more frequently than every other possible access to said storage means.
Claim 4
Dependent Claim
34 words
The interface circuit (2O) of claim 1 wherein a data multiplexer (49) is used to select data from either said receiver means (53) or said processor (22) for writing to said storage means (26).
Claim 5
Dependent Claim
27 words
The interface circuit (2O) of claim 1 wherein said receiver means (53) contains a data pipeline (1O3) for storing, temporarily, the data received from said shared bus.
Claim 6
Dependent Claim
30 words
The interface circuit (2O) of claim 4 wherein said data pipeline (1O3) is a serial device having the capacity to store two bytes of data, in series, at one time.
Claim 7
Dependent Claim
29 words
The interface circuit (2O) of claim 1 wherein said access control means (42, 43) regulates access to said data storage means between the processor and the interface circuit (2O).
Claim 8
Dependent Claim
33 words
The interface circuit (2O) of claim 6 further including a cyclic redundancy check (CRC) circuit (56) for selectively performing error checks on data received from either said processor or said storage means (26).
Claim 9
Dependent Claim
35 words
The interface circuit (2O) of claim 1 wherein said transmitter means (52) contains a data pipeline (97) for storing, temporarily, the data read from the storage means (26) Prior to transmission to the bus (21).
Claim 10
Dependent Claim
29 words
The interface circuit (2O) of claim 8 wherein said data pipeline (97) is a device having the capacity to store two bytes of data, in series, at one time.
Claim 11
Dependent Claim
197 words
1O. An interface circuit (2O), for interfacing between a shared bus (21) and a processor (22), for exchanging data in the form of packets between said bus and said processor, said interface circuit characterized by: interface control means (51, 57) for exchanging control data with said shared bus in order to regulate accesses of said interface circuit to said shared bus; a state machine means (52, 53), including a data pipeline (97, 1O3), said state machine means responsive to control signals from said interface control means, for exchanging data between said shared bus (21) and a data storage means (26); access control means (42, 43) both for controlling the flow of data between said processor (22) and said data storage means (26), and for regulating access to said data storage means (26) between said processor and said state machine means (52, 53); wherein access to said data storage means (26) alternates between said state machine means (52, 53) and said processor (22) such that said data pipeline in said state machine means accommodates data being exchanged between said data storage means and said shared bus during those times that said processor is accessing said data storage means.
Claim 12
Dependent Claim
197 words
1O. An interface circuit (2O), for interfacing between a shared bus (21) and a processor (22), for exchanging data in the form of packets between said bus and said processor, said interface circuit characterized by: interface control means (51, 57) for exchanging control data with said shared bus in order to regulate accesses of said interface circuit to said shared bus; a state machine means (52, 53), including a data pipeline (97, 1O3), said state machine means responsive to control signals from said interface control means, for exchanging data between said shared bus (21) and a data storage means (26); access control means (42, 43) both for controlling the flow of data between said processor (22) and said data storage means (26), and for regulating access to said data storage means (26) between said processor and said state machine means (52, 53); wherein access to said data storage means (26) alternates between said state machine means (52, 53) and said processor (22) such that said data pipeline in said state machine means accommodates data being exchanged between said data storage means and said shared bus during those times that said processor is accessing said data storage means.
Claim 13
Dependent Claim
41 words
The interface circuit (2O) of claim 1O wherein said state machine means (52, 53) includes both a receiver means (53) and a transmitter means (52) and includes two data pipelines (97, 1O3) one for transmit (97) and one for receive (1O3).
Claim 14
Dependent Claim
35 words
The interface circuit (2O) of claim 11 wherein said access control means regulates access to said data storage means (26) such that said processor (22) is given no more than one access in a row.
Claim 15
Dependent Claim
26 words
The interface circuit (2O) of claim 12 wherein each said data pipeline (97, 1O3) contains storage sufficient to data for two accesses to said shared bus.
Claim 16
Dependent Claim
18 words
The interface circuit (2O) of claim 137 wherein each data pipeline (97, 1O3) stores two bytes of data.
Claim 17
Dependent Claim
36 words
The interface circuit (2O) of claim 12 wherein said interface control means responds to polling signals from said shared bus to indicate that said interface circuit requests or does not request access to said shared bus.
Claim 18
Dependent Claim
36 words
The interface circuit (2O) of claim 1O wherein said state machine means (52, 53) is a receive means (53) and includes one data pipeline (1O3) such that the exchange of data is from said bus only.
Claim 19
Dependent Claim
36 words
The interface circuit (2O) of claim 1O wherein said state machine means (52, 53) is a transmitter means (52) and includes one data pipeline (97) such that the exchange of data is to the bus only.
References Cited (Backward Citations)
No citation records indexed.
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