EP0217486A2
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A synchronizing system
Assignee: HP Inc
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Filing: 1986-06-12
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Granted: —
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Expires: 2006-06-12
Abstract
Abstract A synchronizing system is provided for reliably passing data across a boundary between two independent, non-correlated clocks, referredto as the receiving and transmitting clocks. The system reduces occurrence of errors due to asynchronous samplings to an arbitrarily low level based on metastable operation. The system is organized as a two port memory with unit distance code addressing the memory cells. It performs a handshake between the two non-correlated clock systems to allow for any ratio between the two clocks.
Inventors
- 👤 Rasmus Nordby
- 👤 Douglas Crandall
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 15:03
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G06F2205/00; G06F2205/10; G06F2205/102
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
133 words
A synchronizing system comprising: first system means having data synchronized with a first clock signal; second system means having the data to be synchronized with a second clock signal being independent from the first clock signal; and synchronizer means coupled to the first and second system means for transferring the data from the first system means to the second system means, the synchronizer means having a two port memory which receives the data from the first system means at a first address whose succeeding addresses are encoded in a unit distance code by determining that the two port memory is not full, and transmits the data to the second system means from the same address to the first address and the succeeding addresses by determining that the two port memory is not empty.
Claim 2
Dependent Claim
133 words
A synchronizing system comprising: first system means having data synchronized with a first clock signal; second system means having the data to be synchronized with a second clock signal being independent from the first clock signal; and synchronizer means coupled to the first and second system means for transferring the data from the first system means to the second system means, the synchronizer means having a two port memory which receives the data from the first system means at a first address whose succeeding addresses are encoded in a unit distance code by determining that the two port memory is not full, and transmits the data to the second system means from the same address to the first address and the succeeding addresses by determining that the two port memory is not empty.
Claim 3
Dependent Claim
18 words
A synchronizing system according to claim 1, wherein the synchronizer means consists of a one chip integrated circuit.
Claim 4
Dependent Claim
19 words
A synchronizing system according to claim 1, wherein the first clock signal is faster than the second clock signal.
Claim 5
Dependent Claim
20 words
A synchronizing system according to claim 1, wherein the first clock signal is the same as the second clock signal.
Claim 6
Dependent Claim
19 words
A synchronizing system according to claim 1, wherein the first clock signal is slower than the second clock signal.
Claim 7
Dependent Claim
16 words
A synchronizing system according to claim 1, wherein the unit distance code is a Gray code.
References Cited (Backward Citations)
No citation records indexed.
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