Data transfer control unit and system

Claim 2

A data transfer control unit comprising: (a) first address register means (5) for registering a leading address value of a memory area of a memory in to which data to be transferred from an unit is stored; (b) second address register means (23) for registering a final address value of the memory area of the memory into which the data to be transferred is stored; (c) third address register means (11) for registering current address value of data which has already been transferred to the memory area, counting up one by one; and (d) determination means for determining whether or not the address value of the data accessed by a CPU in the course of the data transfer is the address value for the memory area where the data previously transferred is stored.

Claim 3

The data transfer control unit as claimed in claim 1, wherein said determination means is given a construction in which it outputs an unavailability signal when the address value for the data accessed by the CPU in the course of the data transfer falls within the range between the final address value that is set in said second address setting means and the final address value for the transfer completion data that is set in said third address setting means.

Claim 4

The data transfer control unit as claimed in claim 1 wherein said determination means further comprises a first comparator (25) for comparing the final address value registered in said second address register with the address value in question accessed by the CPU in the course of the data transfer and a second comparator (27) for comparing a current address value in said third address register means with the address of data in question accessed by the CPU in the course of the data transfer so as to produce each output signal from said first and second comparators respectively, and a logical circuit (29) for receiving said each output signal from said comparators respectively and for producing a signal indicating that the address of data in question accessed by the CPU in the course of the data transfer belongs to the addresses of the memory area into which the data to be transferred has already been stored or has not yet been stored.

Claim 5

The data transfer control unit as claimed in claim 3, wherein said first comparator produces an output signal when the address of data in question accessed by the CPU in the course of the data transfer is equal to or less than the final address registered in the second address register means, while said second comparator produces an output signal when the address of data in question accessed by the CPU in the course of the data transfer is equal to or larger than the current address value registered in said third address register means.

Claim 6

The data transfer control unit as claimed in claim 4, wherein said logical circuit is an AND circuit.

Claim 7

The data transfer control unit as claimed in claim 1, further comprising a fourth register (17) for registering the number of data units to be transferred and an adder circuit (21) for adding the leading address value registered in the first address register means and the number of data to be transferred, registered in the fourth register so as to set up the resultant sum i.e., the final address value in the second address register means.

Claim 8

The data transfer control unit as claimed in claim 1, further comprising a zero detection circuit for detecting the zero state of the number of data units to be transferred, registered in said fourth register.

Claim 9

The data transfer control unit as claimed in claim 1, further comprising a control unit (3) for controlling the operations of the various registers and data transfer in accordance with various control signals from the CPU.

Claim 10

The data transfer control unit as claimed in claim 6, wherein said third address register means is counted up by one, each time one data transfer is finished while said fourth register is counted down by one, each time one data transfer is finished from a single control signal from said control circuit.

Claim 11

The data transfer control unit as claimed in claim 3, wherein the output of said determination means is connected to the CPU.

Claim 12

A data transfer control system having at least the two data transfer control units, as claimed in claims 1, connected in parallel to each other as well as a CPU, wherein the output of the determination means is connected to each of the control units therein so as to supply a signal indicating that the address of data in question accessed by one control unit or the other control unit belongs to the addresses of the memory areas into which the data to be transferred has not yet been stored.