EP0216161A2 — Digital engine analyzer

Claim 1

Independent Claim 301 words

Apparatus (10) for analyzing analog signals, comprising an analog to digital converter (37, 38) for converting the analog signals into digital signals, memory means (165, 166) for storing the digital signals, a cathode ray tube (11) including a screen and an electron beam which is swept across said screen, said screen being defined by a plurality of rows and a plurality of columns, the electron beam being selectively operable to illuminate selected points at the intersections of the rows and the columns, the electron beam scanning said screen along a row in one row after the next, first means (158a) for monitoring the row in which the electron beam is sweeping at an instant of time (R-S), second means (168) for monitoring the row containing a data point in the column in which the electron beam is located at such instant of time (R-CC), latching means (321) having a clock input coupled to a source of clock signals and a signal input for receiving the R-CC information and latching it until the next column so as to provide information on the row containing a data point in the immediately preceding column (R-PC), and circuit means (322, 323, 324) coupled to said first means and to said second means and to said latching means and being responsive to R-S and R-CC and R-PC to provide a screen energizing signal at each intersection corresponding to the location of a digital signal and to each intersection in a column below a digital signal intersection in such column and above a digital signal intersection in the immediately preceding column and to each intersection in a column above a digital signal intersection in such column and below a digital signal intersection in an immediately preceding column, thereby giving continuity to the waveform displayed on said screen.

Claim 2

Dependent Claim 301 words

Apparatus (10) for analyzing analog signals, comprising an analog to digital converter (37, 38) for converting the analog signals into digital signals, memory means (165, 166) for storing the digital signals, a cathode ray tube (11) including a screen and an electron beam which is swept across said screen, said screen being defined by a plurality of rows and a plurality of columns, the electron beam being selectively operable to illuminate selected points at the intersections of the rows and the columns, the electron beam scanning said screen along a row in one row after the next, first means (158a) for monitoring the row in which the electron beam is sweeping at an instant of time (R-S), second means (168) for monitoring the row containing a data point in the column in which the electron beam is located at such instant of time (R-CC), latching means (321) having a clock input coupled to a source of clock signals and a signal input for receiving the R-CC information and latching it until the next column so as to provide information on the row containing a data point in the immediately preceding column (R-PC), and circuit means (322, 323, 324) coupled to said first means and to said second means and to said latching means and being responsive to R-S and R-CC and R-PC to provide a screen energizing signal at each intersection corresponding to the location of a digital signal and to each intersection in a column below a digital signal intersection in such column and above a digital signal intersection in the immediately preceding column and to each intersection in a column above a digital signal intersection in such column and below a digital signal intersection in an immediately preceding column, thereby giving continuity to the waveform displayed on said screen.

Claim 3

Dependent Claim 132 words

The apparatus of claim 1, wherein said circuit means includes comparator means (322, 323) for comparing R-S with R-CC and with R-PC and providing a comparator signal whenever R-CC equals R-S, or R-CC is greater than R-S, or R-PC equals R-S, or R-PC is greater than R-S, and logic means (324) coupled to said comparator means and being responsive to the comparator signal to provide a screen energizing signal at each intersection corresponding to the location of a digital signal and to each intersection in a column below a digital signal intersection in such column and above a digital signal intersection in the immediately preceding column and to each intersection in a column above a digital signal intersection in such column and below a digital signal intersection in an immediately preceding column.

Claim 4

Dependent Claim 151 words

The apparatus of claim 2, wherein said comparator means includes a first comparator (322) having a first input coupled to said first means (158a) and a second input coupled to said second means (168), said first comparator being operative to produce a logic signal whenever the R-CC information is equal to or greater than the R-S information, and a second comparator (373) having a first input coupled to said first means (158a) and a second input coupled to said latching means (321), said second comparator means being operative to produce a logic signal whenever the R-PC information is equal to or greater than the R-S information, and further latching means (325) having a signal input coupled to said circuit means (322-324) and a control input coupled to a source of clock signals, said further latching means being operative to provide screen energizing signals, thereby to fill in between horizontally adjacent intersections.

Claim 5

Dependent Claim 270 words

Apparatus (10) for analyzing analog signals, comprising an analog to digital converter (37, 38) for converting the analog signals into digital signals, memory means (165, 166) for storing the digital signals, a cathode ray tube (11) including a screen and an electron beam which is swept across said screen, said screen being defined by a plurality of rows and a plurality of columns, the electron beam being selectively operable to illuminate selected points at the intersections of the rows and the columns, such digital signal identifying the row location of a selected point in a different one of the columns, the electron beam scanning said screen along a row in one row after the next, row count means (158a) for providing a row count signal representing the row in which the electron beam is sweeping at an instant of time, the readout means (168) for reading said digital signals out of said memory means in sequence as the electron beam is scanning said screen, signal processing means (321-324) coupled to said memory means and to said row count means and being responsive to the digital signals and the row count signal to provide first signals representing the row locations for the selected points in each column, and second signals representing row locations for points in a given column between the row location for the selected point in said given column and the row location for the selected point in the immediately preceding column, and screen energizing means (325) responsive to said first and second signals for energizing the beam to illuminate the points represented by the first and second signals.

Claim 6

Dependent Claim 270 words

Apparatus (10) for analyzing analog signals, comprising an analog to digital converter (37, 38) for converting the analog signals into digital signals, memory means (165, 166) for storing the digital signals, a cathode ray tube (11) including a screen and an electron beam which is swept across said screen, said screen being defined by a plurality of rows and a plurality of columns, the electron beam being selectively operable to illuminate selected points at the intersections of the rows and the columns, such digital signal identifying the row location of a selected point in a different one of the columns, the electron beam scanning said screen along a row in one row after the next, row count means (158a) for providing a row count signal representing the row in which the electron beam is sweeping at an instant of time, the readout means (168) for reading said digital signals out of said memory means in sequence as the electron beam is scanning said screen, signal processing means (321-324) coupled to said memory means and to said row count means and being responsive to the digital signals and the row count signal to provide first signals representing the row locations for the selected points in each column, and second signals representing row locations for points in a given column between the row location for the selected point in said given column and the row location for the selected point in the immediately preceding column, and screen energizing means (325) responsive to said first and second signals for energizing the beam to illuminate the points represented by the first and second signals.

Claim 7

Dependent Claim 287 words

Apparatus (10) for analyzing analog signals, comprising an analog-to-digital converter (37, 38) for converting the analog signals into digital signals, a cathode ray tube (11) including a screen and an electron beam which is swept across said screen, said screen being defined by a plurality of beam rows and a plurality of beam columns, said screen being further divided into a plurality of character rows and a plurality of character columns defining a plurality of character areas, the electron beam scanning said screen along a row in one row after the next, the electron beam being selectively operable to illuminate selected points at the intersections of the beam rows and the beam columns, monitor means (158a) for monitoring the beam row in which the electron beam is sweeping at an instant of time, character ROM means (157) having stored at a multiplicity of locations therein character matrices respectively corresponding to a multiplicity of characters and respectively being accessed by a multiplicity of character access signals, memory means (154) coupled to said character ROM means for storing character access signals for the character matrices to be displayed in the character areas, character address means (249a-249c) for addressing said memory means with respect to each character matrix one after another in each character row one character row after the other for supplying character matrices corresponding to the characters to be displayed respectively in the character areas, matrix row address means (262) coupled to said character ROM means for causing one row of data for each character matrix selected by said memory means to be simultaneously released, and data generator means (263) coupled to said character ROM means for changing the data simultaneously released therefrom into a sequence of data.

Claim 8

Dependent Claim 287 words

Apparatus (10) for analyzing analog signals, comprising an analog-to-digital converter (37, 38) for converting the analog signals into digital signals, a cathode ray tube (11) including a screen and an electron beam which is swept across said screen, said screen being defined by a plurality of beam rows and a plurality of beam columns, said screen being further divided into a plurality of character rows and a plurality of character columns defining a plurality of character areas, the electron beam scanning said screen along a row in one row after the next, the electron beam being selectively operable to illuminate selected points at the intersections of the beam rows and the beam columns, monitor means (158a) for monitoring the beam row in which the electron beam is sweeping at an instant of time, character ROM means (157) having stored at a multiplicity of locations therein character matrices respectively corresponding to a multiplicity of characters and respectively being accessed by a multiplicity of character access signals, memory means (154) coupled to said character ROM means for storing character access signals for the character matrices to be displayed in the character areas, character address means (249a-249c) for addressing said memory means with respect to each character matrix one after another in each character row one character row after the other for supplying character matrices corresponding to the characters to be displayed respectively in the character areas, matrix row address means (262) coupled to said character ROM means for causing one row of data for each character matrix selected by said memory means to be simultaneously released, and data generator means (263) coupled to said character ROM means for changing the data simultaneously released therefrom into a sequence of data.

Claim 9

Dependent Claim 58 words

The apparatus of claim 5, wherein said matrix row address means addresses the same data in said character ROM means for two consecutive beam rows, said data generator means being clocked at one-half the scanning rate of the electron beam so that each pair of adjacent intersections is illuminated or not, thereby quadrupling the area of each character.

Claim 10

Dependent Claim 210 words

Apparatus (10) for analyzing recurring analog signals each having a portion with a fast rise time, comprising a fast analog to digital converter (38) for relatively rapidly converting analog signals into main digital signals, peak detector means (128) for determining the peak value of the fast rise portion of each analog signal, a slow analog to digital converter (37) for relatively slowly converting the peak values into peak digital signals, storage means for storing the peak digital signals, control means (216) responsive to the occurrence of the fast rise time portion of an analog signal to be displayed to produce an enable signal, gate means (216) having a signal input coupled to said storage means and a control input coupled to said control means, said gate means being responsive to the enable signal to provide the peak digital signal, data means (161-163) having a first input coupled to said fast analog to digital converter and a second input coupled to said gate means and being operative to create a hybrid digital signal in which the peak of the fast rise time portion of the main digital signal is replaced with the peak digital signal, and a cathode ray tube (11) for displaying a waveform corresponding to the hybrid digital signal.

Claim 11

Dependent Claim 210 words

Apparatus (10) for analyzing recurring analog signals each having a portion with a fast rise time, comprising a fast analog to digital converter (38) for relatively rapidly converting analog signals into main digital signals, peak detector means (128) for determining the peak value of the fast rise portion of each analog signal, a slow analog to digital converter (37) for relatively slowly converting the peak values into peak digital signals, storage means for storing the peak digital signals, control means (216) responsive to the occurrence of the fast rise time portion of an analog signal to be displayed to produce an enable signal, gate means (216) having a signal input coupled to said storage means and a control input coupled to said control means, said gate means being responsive to the enable signal to provide the peak digital signal, data means (161-163) having a first input coupled to said fast analog to digital converter and a second input coupled to said gate means and being operative to create a hybrid digital signal in which the peak of the fast rise time portion of the main digital signal is replaced with the peak digital signal, and a cathode ray tube (11) for displaying a waveform corresponding to the hybrid digital signal.

Claim 12

Dependent Claim 62 words

The apparatus of claim 7, wherein said control means is further operative to produce a disable signal in time coincidence with the enable signal, said fast analog to digital converter having a control input coupled to receive the disable signal, said fast analog to digital converter being disabled by the disable signal during the fast rise time portion of each analog signal.

Claim 13

Dependent Claim 196 words

The apparatus of claim 7, and further comprising multiplexer means (110) having a plurality of analog signal inputs respectively coupled to receive the plurality of analog signals, said multiplexer means having a further signal input coupled to said peak detector means, said multiplexer means having first and second outputs respectively coupled to said fast analog to digital converter and to said slow analog to digital converter (38), microprocessor means (151) for providing a plurality of logic signals respectively corresponding to the analog signals, and said multiplexer means having control input means (110a, 110b) coupled to said microprocessor means and being responsive to the selected logic signal to cause the corresponding analog signal to be coupled to said fast analog to digital converter, said microprocessor means providing a microprocessor signal at the time a peak digital signal is to be inserted, further gate means (119) having a signal input coupled to the first output of said multiplexer means and a control input coupled to said microprocessor means and an output coupled to said peak detector means, said further gate means being responsive to the microprocessor signal to couple the corresponding analog signal to said peak detector means.

Claim 14

Dependent Claim 66 words

The apparatus of claim 7, and further comprising means (151) responsive to the fast rise portion of each analog signal to provide an enable signal and a disable signal, said slow analog to digital converter having a control input coupled to said last-mentioned means and being responsive to the enable signal to be rendered operative and being responsive to the disable signal to be rendered inoperative.

Claim 15

Dependent Claim 150 words

Apparatus (10) for analyzing recurring analog signals each having a portion with a fast rise time, comprising a fast analog to digital converter (38) for relatively rapidly converting analog signals into main digital signals, peak detector means (128) for determining the peak value of the fast rise portion of each analog signal, a slow analog to digital converter (37) for relatively slowly converting the peak values into peak digital signals, storage means (115) for storing the peak digital signals, data means (161-163) having a first input coupled to said fast analog to digital converter and a second input coupled to said storage means and being operative to create a hybrid digital signal in which the peak of the fast rise time portion of the main digital signal is replaced with the stored peak digital signal, and display means (11) for displaying a wave form corresponding to the hybrid digital signal.

Claim 16

Dependent Claim 150 words

Apparatus (10) for analyzing recurring analog signals each having a portion with a fast rise time, comprising a fast analog to digital converter (38) for relatively rapidly converting analog signals into main digital signals, peak detector means (128) for determining the peak value of the fast rise portion of each analog signal, a slow analog to digital converter (37) for relatively slowly converting the peak values into peak digital signals, storage means (115) for storing the peak digital signals, data means (161-163) having a first input coupled to said fast analog to digital converter and a second input coupled to said storage means and being operative to create a hybrid digital signal in which the peak of the fast rise time portion of the main digital signal is replaced with the stored peak digital signal, and display means (11) for displaying a wave form corresponding to the hybrid digital signal.

Claim 17

Dependent Claim 226 words

An engine analyzer (10) for analyzing a plurality of recurring analog signals respectively produced by a plurality of cylinders in the engine, each having a portion with a fast rise time, comprising a fast analog to digital converter (38) for relatively rapidly converting analog signals into main digital signals, peak detector means (128) for determining the peak value of the fast rise portion of each analog signal, a slow analog to digital converter (37) for relatively slowly converting the peak values into peak digital signals, signal storage means (201b) including a plurality of registers corresponding in number to the number of cylinders and respectively storing the peak values corresponding to the cylinders, signal combining means (161-163) coupled to said fast analog to digital converter and to said signal storage means and being operative to create a hybrid digital signal in which the peak of the fast rise time portion of the main digital signal is replaced with the peak digital signal, display means for displaying a wave form corresponding to the hybrid digital signal, and monitoring means (227) for monitoring the number of the cylinder which is firing at any instant of time to insure that the peak digital signal being delivered to said signal combining means corresponds to peak value for the cylinder number of the main digital signal applied to said signal combining means.

Claim 18

Dependent Claim 226 words

An engine analyzer (10) for analyzing a plurality of recurring analog signals respectively produced by a plurality of cylinders in the engine, each having a portion with a fast rise time, comprising a fast analog to digital converter (38) for relatively rapidly converting analog signals into main digital signals, peak detector means (128) for determining the peak value of the fast rise portion of each analog signal, a slow analog to digital converter (37) for relatively slowly converting the peak values into peak digital signals, signal storage means (201b) including a plurality of registers corresponding in number to the number of cylinders and respectively storing the peak values corresponding to the cylinders, signal combining means (161-163) coupled to said fast analog to digital converter and to said signal storage means and being operative to create a hybrid digital signal in which the peak of the fast rise time portion of the main digital signal is replaced with the peak digital signal, display means for displaying a wave form corresponding to the hybrid digital signal, and monitoring means (227) for monitoring the number of the cylinder which is firing at any instant of time to insure that the peak digital signal being delivered to said signal combining means corresponds to peak value for the cylinder number of the main digital signal applied to said signal combining means.

Claim 19

Dependent Claim 74 words

The apparatus of claim 12, and further comprising selection means (110) having a plurality of analog signal inputs respectively coupled to receive a plurality of analog signals, said selection means having an output coupled to said signal combining means (161-163), said selection means having control input means coupled to said monitoring means (151) and being responsive to a selected signal therefrom to the associated analog signal to be coupled to said signal combining means.

Claim 20

Dependent Claim 281 words

An engine analyzer (10) for analyzing analog signals produced by the engine, comprising an analog to digital converter (37, 38) for converting the analog signals into digital signals, a cathode ray tube (11) including a screen defined by a plurality of rows and an electron beam which is swept across said screen along a row in one row after the next, waveform means (152) coupled to said analog to digital converter and responsive to the digital signals therefrom to provide waveform data for said cathode ray tube, alphanumeric means (154) for supplying alphanumeric data to said cathode ray tube, monitor means (158a) for monitoring the row in which the electron beam is sweeping at an instant of time, and comparator means (271) having a signal input coupled to said monitor means and having reference input means (271a) connected to constitute a preset reference corresponding to a predetermined row, said comparator means being operative to provide a first control signal when the row in which the electron beam is sweeping is greater than the predetermined row and a second control signal when the row in which the electron beam is sweeping is less than the predetermined row, said waveform means and said alphanumeric means being coupled to said comparator means and being responsive to one of the control signals respectively to become enabled, said waveform means and said alphanumeric means being responsive to the other of the control signals respectively to become disabled and enabled, whereby only alphanumeric data is displayed in the vertical portion of said screen corresponding to the one control signal, and only waveform data is displayed in the portion of the screen corresponding to the other control signal.

Claim 21

Dependent Claim 281 words

An engine analyzer (10) for analyzing analog signals produced by the engine, comprising an analog to digital converter (37, 38) for converting the analog signals into digital signals, a cathode ray tube (11) including a screen defined by a plurality of rows and an electron beam which is swept across said screen along a row in one row after the next, waveform means (152) coupled to said analog to digital converter and responsive to the digital signals therefrom to provide waveform data for said cathode ray tube, alphanumeric means (154) for supplying alphanumeric data to said cathode ray tube, monitor means (158a) for monitoring the row in which the electron beam is sweeping at an instant of time, and comparator means (271) having a signal input coupled to said monitor means and having reference input means (271a) connected to constitute a preset reference corresponding to a predetermined row, said comparator means being operative to provide a first control signal when the row in which the electron beam is sweeping is greater than the predetermined row and a second control signal when the row in which the electron beam is sweeping is less than the predetermined row, said waveform means and said alphanumeric means being coupled to said comparator means and being responsive to one of the control signals respectively to become enabled, said waveform means and said alphanumeric means being responsive to the other of the control signals respectively to become disabled and enabled, whereby only alphanumeric data is displayed in the vertical portion of said screen corresponding to the one control signal, and only waveform data is displayed in the portion of the screen corresponding to the other control signal.

Claim 22

Dependent Claim 34 words

The engine analyzer of claim 14, wherein the first control signal enables said alphanumeric means and disables said waveform means, and the second control signal disables said alphanumeric means and enables said waveform means.

Claim 23

Dependent Claim 93 words

The engine analyzer of claim 14, and further comprising means (12) for placing said engine analyzer in an alphanumeric mode in which only alphanumeric data is displayed on said cathode ray tube, and means (153) responsive to the alphanumeric mode to provide a further control signal, said comparator means being coupled to said last-mentioned means and being responsive to the further control signal to cause the one control signal to be generated irrespective of whether the row in which the electron beam is sweeping is less than or greater than the reference row.

Claim 24

Dependent Claim 169 words

An engine analyzer (10) for analyzing an internal combustion engine that produces engine signals, comprising a cathode ray tube (11) for displaying a waveform corresponding to a selected engine signal which is continuously updated as and when the corresponding electrical signal changes, a keyboard (12) having a key thereon for selecting an RPM setpoint and additional keys for selecting the magnitude of the RPM setpoint, microprocessor means (151) coupled to said keyboard and adapted to process the activation of said keys, said microprocessor operating under stored program for (a) determining the time between ignition signals and converting such time into engine speed in RPM, (b) storing the engine speed in RPM thus calculated, (c) determining whether the engine speed in RPM is equal to or greater than the RPM setpoint, and (d) if so, freezing the waveform on said cathode ray tube to be that corresponding to the electrical signals when the engine speed was at or about the RPM setpoint irrespective of subsequent changes in the electrical signals.

Claim 25

Dependent Claim 169 words

An engine analyzer (10) for analyzing an internal combustion engine that produces engine signals, comprising a cathode ray tube (11) for displaying a waveform corresponding to a selected engine signal which is continuously updated as and when the corresponding electrical signal changes, a keyboard (12) having a key thereon for selecting an RPM setpoint and additional keys for selecting the magnitude of the RPM setpoint, microprocessor means (151) coupled to said keyboard and adapted to process the activation of said keys, said microprocessor operating under stored program for (a) determining the time between ignition signals and converting such time into engine speed in RPM, (b) storing the engine speed in RPM thus calculated, (c) determining whether the engine speed in RPM is equal to or greater than the RPM setpoint, and (d) if so, freezing the waveform on said cathode ray tube to be that corresponding to the electrical signals when the engine speed was at or about the RPM setpoint irrespective of subsequent changes in the electrical signals.

Claim 26

Dependent Claim 214 words

An engine analyzer (10) for analyzing an internal combustion engine that produces engine signals, comprising an analog to digital converter (37, 38) for converting the engine signals into digital signals, main memory means (152) for storing the digital signals and being periodically updated, a cathode ray tube (11) including a screen and an electron beam which is swept across said screen for displaying information stored in said main memory means, freeze memory means (164) for storing the digital signals and being updated at a rate substantially slower than the rate at which said main memory means is updated, switch means (161-163) coupled between said converter and both of said memory means and having an enable condition by which the digital signals are coupled to both of said memory means and a disable condition by which the digital signals are isolated from both of said memory means, generator means (151) for generating a freeze input when digital signals stored in said freeze memory means are to be displayed on said screen, and control means (173) for said freeze memory means and said switch means, said control means being responsive to a freeze input to disable said switch means and enable said freeze memory means to deliver digital signals stored therein to said main memory means.

Claim 27

Dependent Claim 214 words

An engine analyzer (10) for analyzing an internal combustion engine that produces engine signals, comprising an analog to digital converter (37, 38) for converting the engine signals into digital signals, main memory means (152) for storing the digital signals and being periodically updated, a cathode ray tube (11) including a screen and an electron beam which is swept across said screen for displaying information stored in said main memory means, freeze memory means (164) for storing the digital signals and being updated at a rate substantially slower than the rate at which said main memory means is updated, switch means (161-163) coupled between said converter and both of said memory means and having an enable condition by which the digital signals are coupled to both of said memory means and a disable condition by which the digital signals are isolated from both of said memory means, generator means (151) for generating a freeze input when digital signals stored in said freeze memory means are to be displayed on said screen, and control means (173) for said freeze memory means and said switch means, said control means being responsive to a freeze input to disable said switch means and enable said freeze memory means to deliver digital signals stored therein to said main memory means.

Claim 28

Dependent Claim 134 words

An engine analyzer (10) for analyzing an internal combustion engine that produces engine signals, comprising a cathode ray tube (11) for displaying a wave form corresponding to a selected engine signal which is continuously updated as and when the corresponding selected engine signal changes, means (RPM SET POINT) for selecting an RPM setpoint operating mode for the engine analyzer, means (12) for selecting the magnitude of the RPM setpoint, means (151) for determining the time between ignition signals and converting such time into engine speed in RPM, means (115) for storing the engine speed in RPM thus calcu- lated, and means (173) for freezing the wave form displayed on said cathode ray tube to be that corresponding to the selected engine signal which was being produced when the engine speed reaches the RPM setpoint.

Claim 29

Dependent Claim 134 words

An engine analyzer (10) for analyzing an internal combustion engine that produces engine signals, comprising a cathode ray tube (11) for displaying a wave form corresponding to a selected engine signal which is continuously updated as and when the corresponding selected engine signal changes, means (RPM SET POINT) for selecting an RPM setpoint operating mode for the engine analyzer, means (12) for selecting the magnitude of the RPM setpoint, means (151) for determining the time between ignition signals and converting such time into engine speed in RPM, means (115) for storing the engine speed in RPM thus calcu- lated, and means (173) for freezing the wave form displayed on said cathode ray tube to be that corresponding to the selected engine signal which was being produced when the engine speed reaches the RPM setpoint.

Claim 30

Dependent Claim 181 words

An engine analyzer (10) for analyzing an internal combustion engine that produces engine signals comprising display means (111), analog to digital converter means (38) for converting the engine signals to data in the form of wave form data signals for application to said display means for producing a display of wave form patterns, wave form memory means (152) for storing the wave form data signals prior to application to said display means, said wave form memory means including first (165) and second memory (166) banks, memory addressing means coupled to said memory banks for sequentially setting address locations therein to which data is to be written and from which data is to be read, bidirectional data switch means (167, 168) associated with said memory banks, control means (160) for controlling said memory banks, memory addressing means and data switch means to enable data to be written into said first memory bank while data is read from said second memory bank and to enable data to be read from said first memory bank while data is written into said second memory bank.

Claim 31

Dependent Claim 181 words

An engine analyzer (10) for analyzing an internal combustion engine that produces engine signals comprising display means (111), analog to digital converter means (38) for converting the engine signals to data in the form of wave form data signals for application to said display means for producing a display of wave form patterns, wave form memory means (152) for storing the wave form data signals prior to application to said display means, said wave form memory means including first (165) and second memory (166) banks, memory addressing means coupled to said memory banks for sequentially setting address locations therein to which data is to be written and from which data is to be read, bidirectional data switch means (167, 168) associated with said memory banks, control means (160) for controlling said memory banks, memory addressing means and data switch means to enable data to be written into said first memory bank while data is read from said second memory bank and to enable data to be read from said first memory bank while data is written into said second memory bank.

Claim 32

Dependent Claim 148 words

The engine analyzer of claim 20, wherein said memory addressing means includes write address means (212) and read address means (174) which operate asynchronously of one another to enable data to be read from said memory banks at a rate which is many times faster than the rate at which data is written into said memory banks, said display means (11) including a cathode ray tube having a screen and an electron beam which is swept across said screen for displaying information, and display drive means (159) including first timing means (240) for establishing the sweep rate of the beam and the operating rate for said read address means, said converter means (38) operating at a rate correlated to engine speed, said control means including second timing means (204) for controlling the operating rate of said converter means and the operating rate for said write address means (212).

Claim 33

Dependent Claim 63 words

The engine analyzer of claim 21, wherein said control means includes an address counter (225) clocked at the rate at which the digital signals are produced, hardware cylinder couter (227) for providing outputs correlating the electrical signals produced at any instant of time with the corresponding cylinder, and comparator means (236) for comparing the output from the cylinder counter and a selected cylinder.

Claim 34

Dependent Claim 287 words

An engine analyzer (10) for analyzing an internal combustion engine that produces engine signals, comprising display means (11), converter means (38) for deriving data from the engine signals in the form of wave data signals for application to said display means for producing a display of a wave form pattern, wave form memory means (152) for storing the wave form data signals prior to application to said display means, display data means (155) for providing data in the form of display data signals for application to said display means for producing a display of information in at least alphanumeric form, display memory means (154) for storing the display data signals prior to application to said display means, said wave form memory means including first dual bank memory means (165-168) and said display mem ory means including second dual bank memory means (167-171), each of said dual bank memory means including first (A) and second (B) memory banks, memory addressing means (212, 174; 153, 174) coupled to said memory banks for sequentially setting address locations therein to which data is to be written and from which data is to be read, bidirectional data switch means (167, 168-171, 172) associated with said memory banks, control means (160, 173) for controlling associated memory banks, memory addressing means and data switching means to enable data to be written into the first memory bank of a given dual bank memory means while data is read from the second memory bank of said given dual bank memory means, and to enable data to be read from the first memory bank of said given dual bank memory means while data is written into the second memory bank of said given dual bank memory means.

Claim 35

Dependent Claim 287 words

An engine analyzer (10) for analyzing an internal combustion engine that produces engine signals, comprising display means (11), converter means (38) for deriving data from the engine signals in the form of wave data signals for application to said display means for producing a display of a wave form pattern, wave form memory means (152) for storing the wave form data signals prior to application to said display means, display data means (155) for providing data in the form of display data signals for application to said display means for producing a display of information in at least alphanumeric form, display memory means (154) for storing the display data signals prior to application to said display means, said wave form memory means including first dual bank memory means (165-168) and said display mem ory means including second dual bank memory means (167-171), each of said dual bank memory means including first (A) and second (B) memory banks, memory addressing means (212, 174; 153, 174) coupled to said memory banks for sequentially setting address locations therein to which data is to be written and from which data is to be read, bidirectional data switch means (167, 168-171, 172) associated with said memory banks, control means (160, 173) for controlling associated memory banks, memory addressing means and data switching means to enable data to be written into the first memory bank of a given dual bank memory means while data is read from the second memory bank of said given dual bank memory means, and to enable data to be read from the first memory bank of said given dual bank memory means while data is written into the second memory bank of said given dual bank memory means.

Claim 36

Dependent Claim 97 words

The engine analyzer of claim 23, wherein said memory addressing means includes first write address means (212) individually associated with said wave form memory means and second write address means (153) individually associated with said display memory means, said first and second write address means operating at different rates for writing data into said wave form memory means and said display memory means at different rates, and read address means (174) associated with said wave form memory means and with said display memory means for reading data from both of said memory means at the same rate.

Claim 37

Dependent Claim 97 words

The engine analyzer of claim 23, wherein said display data means includes pattern memory means (155) for storing data signals defining a plurality of patterns to be displayed by said display means, and readout means (153, 249) including signal processing (153) means having data registers for storing data representing the information to be displayed an alphanumeric form, said signal processing means being programmed to respond to select signals to read out data signals from said pattern memory means and said data reg isters and to write the data signals thus read out into said display memory means.

Claim 38

Dependent Claim 312 words

An engine analyzer (10) for analyzing an internal combustion engine that produces engine signals, comprising an analog to digital converter (38) for converting the engine signals into digital signals, memory means (152) for storing the digital signals as they are produced, display means (11) for displaying information stored in said memory means, said memory means including first (165) and second (166) memory banks, input data switch means (167) coupled between said converter and both said memory banks and being operable between a first state in which said first memory bank is coupled to said converter and said second memory bank is isolated from said converter and a second state in which said first memory bank is isolated from said converter and said second memory bank is coupled to said converter, output data switch means (168) coupled between both said memory banks and said display means and being operable between a first state in which said first memory bank is isolated from said display means and said second memory bank is coupled to said display means and a second state in which said first memory bank is coupled to said display means and said second memory bank is isolated from said display means, and control means (160) for alternately operating said data switch means between their first and second states, said control means controlling said data switch means and said memory means for alternately switching said data switch means between their first and second states to enable data to be written into said first memory bank while data is read from said second memory bank and to enable data to be read from said first memory bank while data is written into said second memory bank, the rate at which data is read from said memory banks being many times faster than the rate at which data is written into said memory banks.

Claim 39

Dependent Claim 312 words

An engine analyzer (10) for analyzing an internal combustion engine that produces engine signals, comprising an analog to digital converter (38) for converting the engine signals into digital signals, memory means (152) for storing the digital signals as they are produced, display means (11) for displaying information stored in said memory means, said memory means including first (165) and second (166) memory banks, input data switch means (167) coupled between said converter and both said memory banks and being operable between a first state in which said first memory bank is coupled to said converter and said second memory bank is isolated from said converter and a second state in which said first memory bank is isolated from said converter and said second memory bank is coupled to said converter, output data switch means (168) coupled between both said memory banks and said display means and being operable between a first state in which said first memory bank is isolated from said display means and said second memory bank is coupled to said display means and a second state in which said first memory bank is coupled to said display means and said second memory bank is isolated from said display means, and control means (160) for alternately operating said data switch means between their first and second states, said control means controlling said data switch means and said memory means for alternately switching said data switch means between their first and second states to enable data to be written into said first memory bank while data is read from said second memory bank and to enable data to be read from said first memory bank while data is written into said second memory bank, the rate at which data is read from said memory banks being many times faster than the rate at which data is written into said memory banks.

Digital engine analyzer

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