System for controlling a data transfer instruction with an extension storage device

Abstract

Abstract The invention relates to a system for controlling a data transfer instruction in a computer apparatus having a processor unit (3), a main storage unit (1) for storing data to be processed by the processor unit, and an extension storage unit (5) for supplying data to the main storage unit. The system comprises an address control circuit (42) for holding a beginning designating logical address for designating the beginning of a storage region of the extension storage unit, a beginning designating logical address for designating the beginning of a storage region of the main storage unit, and a designation of a transfer mode, which are designated by a data transfer instruction to be executed by the processor unit. An adder (4232) sums pitch distances corresponding to the designation of the transfer mode, and, accordingly, generates a logical address to be accessed for the extension storage unit from a logical address of the extension storage unit. An address conversion circuit (41) converts the logical address to be accessed to the beginning designating real address for the extension storage unit. A second address conversion circuit (44) converts the logical address produced from the beginning designating logical address of the main storage unit to the beginning designating real address for the main storage unit. Data transfer is executed between a storage region of the extension storage device designated by the beginning designating real address for the extension storage unit and a storage region of the main storage unit designated by the beginning designating real address for the main storage unit.

Inventors

• 👤 Akira Yoshida
• 👤 Tetsuro Okamoto

Bibliographic Details