Bus driver circuit

Claim 2

An integrated circuit tri-state bus driver circuit comprising: a first MOS transistor (28) whose source is connected to an outlet terminal connected to the bus to be driven, and whose drain is connected to a voltage source; a second transistor (30) whose source is connected to ground potential and whose drain is connected to the outlet terminal; a third transistor (24) whose source is connected to the gate of the first transistor (28); a fourth transistor (26) whose source is connected to the gate of the second transistor (30); the drains of the third and fourth transistors being connected to a system clock signal, a first buffer (20) whose outlet is connected to the gate of the third transistor (24); a second buffer (22) whose outlet is connected to the gate of the fourth transistor (26); the inlet to the first buffer (20) being connected to a source of two-level binary data signals, and the inlet to the second buffer (22) being connected to a source of two-level binary data signals complementary to the binary data signals connected to the inlet of the first buffer (20).

Claim 3

The bus driver circuit as claimed in Claim 1, further including a first AND gate (34) whose outlet is connected to the inlet of ther first buffer (20) and which has first and second inlets, the first inlet being connected to the source of binary data signals, and the second inlet being connected to a source of data enable control signals.

Claim 4

The bus driver circuit as claimed in Claim 2, further including a second AND gate (35) whose outlet is connected to the inlet of the second buffer (22) and which has first and second inlets, the first inlet being coupled to the source of binary data signals via an inverter (32), and the second inlet of the second buffer (22) being connected to the source of data enable control signals.

Claim 5

The bus driver circuit as claimed in Claim 3, wherein the first and second buffers (20, 22) are of the push-pull operating type.

Claim 6

A tri-state integrated circuit bus driver circuit comprising first and second complementary output MOS transistors (28,30) coupled to an outlet terminal, which terminal is connected to the bus to be driven, the first transistor (28) being connected to a voltage source, and the second transistor being connected to ground, such that the terminal, upon selective enabling of the output transistors, will have applied to it the voltage source, the ground potential, or an open-circuit condition, first and second bootstrap MOS transistors (24,26) connected to the first and second output transistors (28,30), respectively, and also connected to a common system clock signal, such that when the first bootstrap transistor (24) is enabled, the first output transistor (28) is also, enabled thereby connecting the voltage source to the outlet terminal, and when the second bootstrap transistor (26) is enabled, the second output transistor (30) is also enabled, thereby applying ground potential to the outlet terminal, and when neither bootstrap transistor (24,26) is enabled, neither output transistor (28,30) is conducting and an open-­circuit, or high impedance, is applied to the outlet terminal, first and second buffers (20, 22) connected to the first and second bootstrap transistors (24, 26), the buffers being connected to a source of binary data signals and their complementary binary data signals, respectively, such that when binary data are transferred to the first and second bootstrap transistors (24,26), the output signals at the outlet terminal will be the tri-state digital signals, of duration and period dependent on the duration and period of the system clock signal.

Claim 7

A tri-state integrated circuit bus driver circuit comprising first and second complementary output MOS transistors (28,30) coupled to an outlet terminal, which terminal is connected to the bus to be driven, the first transistor (28) being connected to a voltage source, and the second transistor being connected to ground, such that the terminal, upon selective enabling of the output transistors, will have applied to it the voltage source, the ground potential, or an open-circuit condition, first and second bootstrap MOS transistors (24,26) connected to the first and second output transistors (28,30), respectively, and also connected to a common system clock signal, such that when the first bootstrap transistor (24) is enabled, the first output transistor (28) is also, enabled thereby connecting the voltage source to the outlet terminal, and when the second bootstrap transistor (26) is enabled, the second output transistor (30) is also enabled, thereby applying ground potential to the outlet terminal, and when neither bootstrap transistor (24,26) is enabled, neither output transistor (28,30) is conducting and an open-­circuit, or high impedance, is applied to the outlet terminal, first and second buffers (20, 22) connected to the first and second bootstrap transistors (24, 26), the buffers being connected to a source of binary data signals and their complementary binary data signals, respectively, such that when binary data are transferred to the first and second bootstrap transistors (24,26), the output signals at the outlet terminal will be the tri-state digital signals, of duration and period dependent on the duration and period of the system clock signal.

Claim 8

The bus driver circuit as claimed in Claim 5, further includin a first AND gate (34) whose outlet is connected to the first buffer (20); a second AND gate (35) whose outlet is connected to the second buffer (22) and a data control signal connected to an inlet of both the AND gates (34,35) such that the binary data signals or their complements are transferred to the first and second buffers (20,22) only upon enabling of the AND gates (34,35) by the data control signal, the output on the bus being a tri-state signal comprising a digital one, a digital zero, or a no-signal, -high impedance state.