Adaptive packet/circuit switched transportation method and system

Claim 2

Method for configuring a succession of complex frames to be used for exchanging synchronous circuit switched bits and asynchronous packet switched bits between nodes connected through medium links working at any bit rates in a teleprocessing network, characterized in that: each complex frame which contains an integer number of bits equal to Nc or Nc+1 chosen as close as possible to a predetermined number Na (256), is made of a succession of subframes and delimited by flags, in such a way that the period between two flags is equal to nT+e, T being the period of existing Time Division Multiplex Frames (125 microseconds) and n being an integer number bits higher or equal to 1 which depends upon the medium link bit rate and e being lower than a medium link bit period, the subframes have a duration less or equal to T, each subframe i containing an integer number Nsi of bits, said integer number being allocated to carry an integer number of circuit switched bit slots and the remaining bits being used to carry asynchronous packet switched bits, the R bits remaining in the complex frame, with being used to carry F flag bits and r=R-F padding bits which are used to carry asynchronous packet switched bits.

Claim 3

Method according to claim 1, characterized in that it comprises the following step: calculating the medium link bit period t as a function of the bit rate on the medium link on which the frame is to be generated, calculating the theoratical integer number Nts of bits in period T calculating n which is the integer part of Na/Nts calculating the residual bit number R=n(T/t -Nts) comparing R with the desired number of flag bits f, if R is higher than f, Ns is made equal to Nts, if not Ns is made equal to Nts -1 and the new corresponding value of residual bits R1=n(T/t-(Nts-1) is calculated.

Claim 4

Method according to claim 2 characterized in that all the subframes in the complex frames contain a constant number Ns of bits.

Claim 5

Method according to claim 2 characterized in that at least one of the residual bit is placed in a given subframe so that the subframes contain a variable bit number Nsi.

Claim 6

Method according to any one of claim 1 to 4, characterized in that the flag contain two delimiting bits which are set to opposite values.

Claim 7

Method according to claim 5 characterized in that the bit user slot are dynamically allocated in the complex frame by coding the f-2 remaining bit of the flag of at least the first complex frame wherein the slot allocation is to be changed to a value indicating that a slot is to be added or deleted and the slot number which is to be added or deleted.

Claim 8

System for implementing the method according any one of claims 1 to 5 characterized in that it comprises in the transmitting means which are connected to the transmit interface of the medium link: medium access managing means (20) for processing the link parameters (Nc, n and Ns) and defining the circuit user slot allocation, means for generating system control signals (32) setting the transmitting means in disabled, initial or operational mode, medium link clock means (48) providing clock pulses at the medium link bit rate, first storing means (22) wherein the medium access managing means loads the Ns value, second storing means (24) wherein the medium access managing means loads the n value, third storing means (26) wherein the medium access managing means loads a slot table indicating whether the subframe slots contain circuit switched bits or packet switched bits, subframe generation control means (47,44,52) operating under the control of the medium link clock means and of the first storing means so as to provide a signal controlling the generation of the successive subframes in the complex frames, complex frame generation control means (46,49,54) operating under control of the subframe generation control means and of the second storing means so as to provide a signal controlling the generation of the n successive subframes of each complex frames, T counting means (57) counting pulses of period T nT boundary indicating means (200) sensitive to the T counting means and to the second storing means content for providing signals indicative of the nT boundaries, flag generating means (228, 230) responsive to the system control signals, first logic means (56) for generating: -a r sending control signal (60) under control of the complex frame generation control means, said signal being active at the end of the last subframe of the complex frame until the next nT boundary indication provided by the nT boundary indicating means, -a next slot control signal (70) which is active at each s bit (s=8) boundary, s being the number of bits contained in a slot, during the subframe generation, for scanning the slot table in third storing means, -a flag sending control signal (68) which is active at the bit time following the detection of a nT boundary during f bit periods, for activating the flag generating means so as to send the flag delimiting the complex frame, second logic means (30) which are responsive to the system control signals, to the r sending signal, to the signals controlling the generation of the subframes and of the complex frames, and to the scanning of the slot table for generating enable signals which control the sending of circuit switched bits or packet switched bits on the transmit interface of the medium link.

Claim 9

System for implementing the method according to claim 6 characterized in that it comprises in the transmitting means which are connected to the transmit interface of the medium link: medium access managing means (20) for processing the link parameters (NC, n and Ns) and defining the circuit user slot allocation, means for generating system control signals (32) setting the transmitting means in disabled, initial or operational mode, medium link clock means (48) providing clock pulses at the medium link bit rate, first storing means (22) wherein the medium access managing means loads the Ns value, second storing means (24) wherein the medium access managing means loads the n value, third storing means (26) wherein the medium access managing means loads a slot table indicating whether the subframe slots contain circuit switched bits or packet switched bits, said slot table being updated when circuit switched bit slot have to be added or deleted in the subframes of a complex frame, subframe generation control means (47,44,52) operating under the control of the medium link clock means and of the first storing means so as to provide a signal controlling the generation of the successive subframes in the complex frames, complex frame generation control means (46,49,54) operating under control of the subframe generation control means and of the second storing means so as to provide a signal controlling the generation of the n successive subframes of each complex frames, T counting means (57) counting pulses of period T nT boundary indicating means (200) sensitive to the T counting means and to the second storing means content for providing signals indicative of the nT boundaries, flag generating means (228, 230) responsive to the system control signals, and to the medium access managing means which set the f-2 bits of the flag preceding the complex frame to a value indicating that a slot is to be added or deleted in the following complex frames and the number of the slot to be added or deleted, so that different configurations of flags are sent depending upon the system control signals and the setting of the f-2 bits of the flag, first logic means (56) for generating: -a r sending control signal (60) under control of the complex frame generation control means, said signal being active at the end of the last subframe of the complex frame until the next nT boundary indication provided by the nT boundary indicating means, -a next slot control signal (70) which is active at each s bit (s=8) boundary, s being the number of bits contained in a slot, during the subframe generation, for scanning the slot table in third storing means, -a flag sending control signal (68) which is active at the bit time following the detection of a nT boundary during f bit periods, for activating the flag generating means so as to send one of the flag configurations, second logic means (30) which are responsive to the system control signals, to the r sending signal, to the signals controlling the generation of the subframes and of the complex frames, and to the scanning of the slot table for generating enable signals which control the sending of circuit switched bits or packet switched bits on the transmit interface of the medium link.

Claim 10

System according to claim 7 characterized in that the receiving means connected to the receive interface of the link comprises: a medium access managing means (100) for proessing the medium link parameters (Nc, n, Ns), means (101) for generating system control signals which depend upon the operational state of the system, first storing means (102) in which the medium access managing means loads the Ns parameter, second storing means (104) in which the medium access managing means loads the n parameter, third storing means (106) in which the medium access managing means loads a slot table indicating whether the subframe slots contain circuit switched bits or packet switched bits, medium link clock means (112) which provides clock pulses at the bit rate, f-bit shifting register means, connected to the receive interface of the link in which the received bits are inputted, first logic means (128) for counting the received bits and detecting the delimiting bits of the flags, said means operating under control of the medium link clock means, and providing a flag period signal (130) which is active during f bit period following the flag detection providing a resetting control signal during the flag detection, a r received signal (130) and a next slot signal (137) which is active at the s bit boundary except during the flag detection and when the r received signal is active, said next slot signal controlling the scanning of the slot table, subframe receiving control means (108,114,140) operating under the control of the medium link clock and of the resetting control signal, to provide a signal which is active during the received subframe duration, complex frame receiving control means (110,116,142) operating under the control of the subframe receiving control means and to the resetting control signal, to provide a signal which is active during the n received subframe duration, said signal being provided to the first logic means so as to cause the r received signal to be active at the end of the n subframes until the flag detection, second logic means (118) which generates from the signals provided by the subframe receiving control means and the complex frame receiving control means, from the flag period signal, from the r received signal and from the scanning of the slot table, packet or circuit switched bit enable signals which are active to have the received bits at the output of the f bit-shifting register processed as packet switched bits or circuit switched bits.

Claim 11

System according to claim 8 characterized in that the receiving means connected to the receive interface of the link comprises: a medium access managing means (100) for processing the medium link parameters (Nc, n, Ns), means (101) for generating system control signals which depend upon the operational state of the system, first storing means (102) in which the medium access managing means loads the Ns parameter, second storing means (104) in which the medium access managing means loads the n parameter, third storing means (106) in which the medium access managing means loads a slot table indicating whether the subframe slots contain circuit switched bits or packet switched bits, medium link clock means (112) which provides clock pulses at the bit rate, f-bit shifting register means, connected to the receive interface of the link in which the received bits are inputted, first logic means (128) for counting the received bits and detecting the delimiting bits of the flags, said means operating under control of the medium link clock means, and providing a flag period signal (130) which is active during f bit period following the flag detection providing a resetting control signal during the flag detection, a r received signal (130) and a next slot signal (137) which is active at the s bit boundary except during the flag detection and when the r received signal is active, said next slot signal controlling the scanning of the slot table, and detecting the f-2 received flag bits so as to update the slot table when said flag bits indicate that a circuit switched bit slot is to be added or deleted, subframe receiving control means (108,114,140) operating under the control of the medium link clock and of the resetting control signal, to provide a signal which is active during the received subframe duration, complex frame receiving control means (110,116,142) operating under the control of the subframe receiving control means and to the resetting control signal, to provide a signal which is active during the n received subframe duration, said signal being provided to the first logic means so as to cause the r received signal to be active at the end of the n subframes until the flag detection, second logic means (118) which generates from the signals provided by the subframe receiving control means and the complex frame receiving control means, from the flag period signal, from the r received signal and from the scanning of the slot table, packet or circuit switched bit enable signals which are active to have the received bits at the output of the f bit-shifting register processed as packet switched bits or circuit switched bits.

Claim 12

System according to any one of claim 7 to 10 characterized in that it comprises: means (82,38,80) for sending an idle configuration (1111..11) during the disabled state of the system means (90,92,94,80) for sending the idle configuration delimited by flags during the initial period, the number of ones which are sent between two flags being equal to Nc on Nc+1.

Claim 13

System according to any one of claims 7 to 11 characterized in that the subframe generation control means in the transmitting means comprises: bit counting means (44) which counts the clock pulses provided by the medium link clock (48), comparing means (47) which compares the content of the bit counting means (44) and of the first storing means (22), resetting means (50) which provides a reset control signal to the bit counting means when an equality is detected by said comparing means or when the flag sending signal is active, whereby the output signal of said first comparing means is active during the subframe generation periods.

Claim 14

System according to claim 12 characterized in that the complex frame generation means in the transmitting means comprises: subframe counting means (46) which counts the subframes under control of the first comparing means (47), comparing means (49) which compares the content of the subframe counting means and of the first storing means, resetting means (54) which provides a reset control signal for resetting the subframe counting means when an equality if detected by said second comparing means or when the flag sending signal is active, whereby the output of said second comparing means is active during the n subframe generation period of the complex frames.

Claim 15

System according to any one of claim 9 to 13 characterized in that the subframe receiving control means in the receiving means comprises: bit counting means (108) which counts the clock pulses provided by the medium link clock means (112) comparing means (114) which compares the content of the bit counting means (108) and of the first storing means (22), resetting means (140) which provides a reset control signal when an equality is detected by said comparing means or during the flag detection period, whereby the output signal of said comparing means is active during the subframe reception periods.

Claim 16

System according to claim 14 characterized in that the complex frame receiving control means in the receiving means comprises: subframe counting means (110) which counts the subframes under control of the comparing means of the subframe receiving control means, comparing means (116) which compares the content of the subframe counting means and of the second storing means resetting means (142) which provides a reset control signal for resetting the subframe counting means when an equality is detected by said comparing means or during the flag detection period whereby the output of said comparing means is active during the n subframe reception period of the complex frames.

Claim 17

System according to any one of claims 11 to 15 characterized in that the receiving means comprises: specific flag detecting means (300) which are active during the initialization period under control of the means for generating the system control signals medium bit counting means (320) for counting the medium link clock pulses provided by the medium link clock means (112) between two flags, means (326,322) for storing the number of pulses which are counted by the medium bit counting means during two flags of the initialization period, said number (Nc or Nc+1) being used by the medium access manager to compute the link parameters.