EP0213955A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Circuit for simultaneously obtaining in parallel signals constituting a time division multiplexed signal
Assignee: Victor Company of Japan Ltd
•
Filing: 1986-09-02
•
Granted: —
•
Expires: 2006-09-02
Abstract
Abstract A circuit for simultaneously obtaining in parallel signals constituting a time division multiplexed signal comprises a first delay circuit (20) supplied with an input time division multiplexed signal and having a delay time corresponding to a duration of one of the signals constituting the time division multiplexed signal, a switching circuit (2l) supplied with an output signal of the first delay circuit and the input time division multiplexed signal for carrying out a switching operation for every constant repetition period so as to simultaneously output signals in parallel, a second delay circuit (33) supplied with the output signal of the first delay circuit and having a delay time identical to that of the first delay circuit, an operation circuit (34) supplied with the input time division multiplexed signal and an output signal of the second delay circuit for carrying out a subtraction or an addition, and a non-linear characteristic circuit (35, 32, 4l-43) having an input versus output characteristic which varies non-linearly. The non-linear characteristic circuit is supplied with an output signal of the operation circuit and feeds back an output signal thereof to the time division multiplexed signal.
Inventors
- 👤 Kazuhiko Ueda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 10:05
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/40; H04N25/44; H04N25/447; H04N25/10; H04N25/11
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
227 words
A circuit for simultaneously obtaining in parallel signals constituting a time division multiplexed signal, said circuit comprising a first delay circuit (20) supplied with an input time division multiplexed signal and having a delay time corresponding to a duration of one of the signals constituting said time division multiplexed signal, said time division multiplexed signal having been time-division-multiplexed with a constant repetition period corresponding to that of a television signal and having correlation for every said repetition period, and a switching circuit (2l) supplied with an output signal of said first delay circuit and said input time division multiplexed signal for carrying out a switching operation every said constant repetition period so as to simultaneously output signals in parallel, characterized in that there are provided: a second delay circuit (33) supplied with the output signal of said first delay circuit and having a delay time identical to that of said first delay circuit; an operation circuit (34) supplied with said input time division multiplexed signal and an output signal of said second delay circuit for carrying out a subtraction or an addition; and non-linear characteristic circuit means (35, 32, 4l-43) having an input versus output characteristic which varies non-linearly, said non-linear characteristic circuit means being supplied with an output signal of said operation circuit and feeding back an output signal thereof to said time division multiplexed signal.
Claim 2
Dependent Claim
227 words
A circuit for simultaneously obtaining in parallel signals constituting a time division multiplexed signal, said circuit comprising a first delay circuit (20) supplied with an input time division multiplexed signal and having a delay time corresponding to a duration of one of the signals constituting said time division multiplexed signal, said time division multiplexed signal having been time-division-multiplexed with a constant repetition period corresponding to that of a television signal and having correlation for every said repetition period, and a switching circuit (2l) supplied with an output signal of said first delay circuit and said input time division multiplexed signal for carrying out a switching operation every said constant repetition period so as to simultaneously output signals in parallel, characterized in that there are provided: a second delay circuit (33) supplied with the output signal of said first delay circuit and having a delay time identical to that of said first delay circuit; an operation circuit (34) supplied with said input time division multiplexed signal and an output signal of said second delay circuit for carrying out a subtraction or an addition; and non-linear characteristic circuit means (35, 32, 4l-43) having an input versus output characteristic which varies non-linearly, said non-linear characteristic circuit means being supplied with an output signal of said operation circuit and feeding back an output signal thereof to said time division multiplexed signal.
Claim 3
Dependent Claim
76 words
A circuit as claimed in claim l, characterized in that said non-linear characteristic circuit means (35, 32) comprises a non-linear amplifier (35) supplied with the output signal of said operation circuit and having a non-linear input versus output characteristic, and an adder (32) for adding an output signal of said non-linear amplifier to said input time division multiplexed signal and for supplying an output signal thereof to said first delay circuit and to said switching circuit.
Claim 4
Dependent Claim
139 words
A circuit as claimed in claim l, characterized in that said non-linear characteristic circuit means (32, 4l-43) comprises an absolute value circuit (43) supplied with the output signal of said operation circuit and having a non-linear input versus output characteristic, a first variable gain amplifier (4l) supplied with said input time division multiplexed signal and having a gain thereof varied responsive to an output signal of said absolute value circuit, a second variable gain amplifier (42) supplied with the output signal of said second delay circuit and having a gain thereof varied responsive to the output signal of said absolute value circuit, and an adder (32) supplied with output signals of said first and second variable gain amplifiers for carrying out an addition and supplying an output signal thereof to said first delay circuit and to said switching circuit.
Claim 5
Dependent Claim
89 words
A circuit as claimed in claim 3, characterized in that said first variable gain amplifier (4l) multiplies a gain (l-K) to said input time division multiplexed signal and said second variable gain amplifier (42) multiplies a gain K to the output signal of said second delay circuit, said gains of said first and second variable gain amplifiers being controlled by the output signal of said absolute value circuit so that a value of K becomes small when an output signal value of said operation circuit exceeds a threshold value.
Claim 6
Dependent Claim
54 words
A circuit as claimed in claim l, characterized in that said input time division multiplexed signal is a line-sequential color difference signal, said first and second delay circuits (20, 33) having a delay time corresponding to one horizontal scanning period, said switching circuit carrying out the switching operation for every one horizontal scanning period.
Claim 7
Dependent Claim
58 words
A circuit as claimed in claim 5, characterized by being used in an image pickup device comprising a solid state image sensor (ll) provided with a complementary color filter (l2) on a front surface thereof and circuit means (l5a, l5b, l6-l8) for obtaining the line-sequential color difference signal from an output signal of said solid state image sensor.
References Cited (Backward Citations)
EP0145297A2
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.