Patent US4782945A successfully refreshed from Google Patents.
EP0213641A2
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Delay time adjusting method, circuit, and system
Assignee: Fujitsu Ltd
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Filing: 1986-09-04
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Granted: —
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Expires: 2006-09-04
Abstract
Abstract In a delay time adjusting circuit, a transmitter device divides original data into a first data signal and a second data signal and sends the first data signal and the second data signal via different transmission paths to a receiving device, and the receiving device mixes the first data signal and the second data signal so as to reproduce the original data. In the receiving device, the first data signal is written in first elastic memory (101) and is operated in response to a clock of the first data signal, the second data signal is delayed and corresponding bits of the first elastic memory (101) are sequentially read out in response to an output of a ring counter (104) having the same number of bits as that of the first elastic memory (101) and operated in response to a clock of the second signal, and to which the position of the first data signal in the first elastic memory (101) is loaded in response to the delayed second data signal.
Inventors
- 👤 Takashi Sakata
- 👤 Toshio Hanabata
- 👤 Naonobu Fujimoto
- 👤 Tetsuro Murase
- 👤 Fumihiro Ikawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 14:43
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/14; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H04J3/0629
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
170 words
I. A delay time adjusting method in which a transmitter device divides original data into a first data signal and a second data signal and sends said first data signal and said second data signal via different transmission paths to a receiving device, and said receiving device mixes said first data signal and said second data signal so as to reproduce said original data, characterized in that in said receiving device, said first data signal is written in first elastic memory and is operated in response to a clock of said first data signal, said second data signal is delayed and corresponding bits of said first elastic memory are sequentially read out in response to an output of a ring counter having the same number of bits as that of the first elastic memory and operated in response to a clock of the second signal, and to which the position of the first data signal in the first elastic memory is loaded in response to the delayed second data signal.
Claim 2
Dependent Claim
216 words
A delay time adjusting circuit in a signal transmission system in which a high-speed data signal is divided into two low-speed data signals, the low-speed signals are transmitted through different transmission paths, and after a difference in delay times between the two signals is absorbed at a reception side, the low-speed signals are mixed again, characterized in that a first signal and a sync signal synchronous therewith are simultaneously written in first and second elastic memories (101, 102) having the same bit length and are operated in response to a clock of the first signal; a second signal and a sync signal synchronous therewith are delayed by the same time period by a fixed delay circuit (103); the position of the first sync signal in said second elastic memory is loaded, in response to the delayed second sync signal, in a counter (104) having the same number of bits as that of said first and second elastic memories and operated in response to a clock of the second signal; and corresponding bits of said first elastic memory are sequentially read out through a data selector (105) in response to the output from said counter, thereby obtaining a first signal output, from which the difference in the delay times with respect to the second signal is absorbed.
Claim 3
Dependent Claim
261 words
A delay time adjusting system in which the phases of first and second inputs of third multiplexed data having a phase difference of ±B bits and in which said first input consisting of a bipolar signal is converted to a unipolar signal by a first bipolar/unipolar converter (31), and a high density bipolar (HDB3) code is decoded by a first HDB3 decoder (32), thus producing a 34 MHz clock signal as well as a 34-Mb/sec data signal, a first demultiplexer (33) demultiplexes these signals and produces eight 4-Mb/sec data signals, a 4 MHz clock signal, and a frame signal said eight data signals and said frame signal are delayed through nine D/8-bit delay circuits in a fixed delay circuit - (34), and a first data signal is output as output data DATA OUTI, and a second data input similarly passes through a second bipolar/unipolar converter, a second HDB3 decoder (36), and a second demultiplexer (37), thus producing eight 4-Mb/sec data signals, a 4 MHz clock signal, and a frame signal, said eight data signals and said frame signal are input to a variable delay circuit (38), and are delayed through nine D/4-bit delay circuits, characterized in that said variable delay circuit receives the 4 MHz clock signal from said second demultiplexer (37) as a write clock, the 4 MHz clock signal from said first demultiplexer (33) as a read clock, and the frame signal passing through said fixed delay circuit (34) as a delayed sync signal, thereby producing output data DATA OUT2 which is phase-locked with the output data DATA OUTI.
References Cited (Backward Citations)
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