EP0212946A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1986-08-13
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Granted: —
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Expires: 2006-08-13
Abstract
Abstract A complementary semiconductor memory device comprises a memory cell array (73; 100) in which each cell (MCp; MC po ) has a first MIS transistor (Qp; Qp 1 , Qp 2 ) of a first conduction type connected to a word line, a decoding circuit (71) for decoding an input address signal and generating a selecting signal, and a driving circuit (72; 90) having a second MIS transistor (Q 80 ) of a second conduction type opposite to the first conduction type for driving the word line, thereby improving the operation speed thereof, while decreasing the possibility of the destruction of information in each cell by a-rays.
Inventors
- 👤 Tomio Nakano
- 👤 Yoshihiro Takemae
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 21:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C8/00; G11C8/08; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4085; G11C5/00; G11C5/005; G11C8/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
115 words
A complementary semiconductor memory device comprising: a memory cell array (73; 100), each cell (MC ; MC ) having a first MIS transistor (Q Q p1 Q p2 ) of a first conduction type constituting an access or transfer gate,connected to a respective one of a plurality of word lines; a decoding circuit (71) for decoding an address signal input, and based on a result of said decoding, generating a selecting signal; and a driving circuit (72; 90) having a second MIS transistor (Q 80 ) of a second conduction type opposite to said first conduction type for selecting a specific word line among said plurality of word lines in response to said selecting signal.
Claim 2
Dependent Claim
115 words
A complementary semiconductor memory device comprising: a memory cell array (73; 100), each cell (MC ; MC ) having a first MIS transistor (Q Q p1 Q p2 ) of a first conduction type constituting an access or transfer gate,connected to a respective one of a plurality of word lines; a decoding circuit (71) for decoding an address signal input, and based on a result of said decoding, generating a selecting signal; and a driving circuit (72; 90) having a second MIS transistor (Q 80 ) of a second conduction type opposite to said first conduction type for selecting a specific word line among said plurality of word lines in response to said selecting signal.
Claim 3
Dependent Claim
52 words
A device according to claim 1, wherein said first MIS transistor (Q p ; Q p1 , Q p2 ) in each cell of said memory cell array (73; 100) is a P-channel type, and said second MIS transistor (Q 80 ) in said driving circuit (72; 90) is an N-channel type.
Claim 4
Dependent Claim
32 words
A device according to claim 2, wherein said driving circuit (90) further comprises a third P-channel type MIS transistor (Q 90 ) connected complementarily to said second MIS transistor (Q 80 ).
Claim 5
Dependent Claim
27 words
A device according to claim 1 2 or 3,wherein each cell (MC ) in said memory cell array (73) is a dynamic type RAM structure. 3 ,
Claim 6
Dependent Claim
26 words
A device according to claim 1, 2 or 3 wherein each cell (MC ) in said memory cell array (100) is a static type RAM structure.
Claim 7
Independent Claim
61 words
A device according to any preceding claim , wherein said decoding circuit (71) comprises a decoder (71A) and a predecoder (71B), said decoder being operable to generate a first signal for selecting a group of word lines including said specific word line, said predecoder being operable to generate a second signal for activating said specific word line at a predetermined timing.
Claim 8
Dependent Claim
29 words
A device according to claim 6, wherein said is operable to driving circuit (72; 90)/transmit said second signal to said specific word line in response to said first signal.
References Cited (Backward Citations)
No citation records indexed.
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