Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
128 words
A clock signal generating circuit for a dynamic type semiconductor memory device comprising: an input voltage level control means for converting a first drive level to a second drive level during transmission of an address strobe signal, an address buffer control means for generating an address signal in response to a trailing edge of the address strobe signal, a clock signal generating means for generating a clock signal used for word line selection and an input signal for a next stage in response to a low level of the address strobe signal, and driving an inhibiting means for inhibiting / of the word line by the clock signal when the a address strobe signal is at/high level at a timing of a leading edge of the clock signal.
Claim 2
Dependent Claim
128 words
A clock signal generating circuit for a dynamic type semiconductor memory device comprising: an input voltage level control means for converting a first drive level to a second drive level during transmission of an address strobe signal, an address buffer control means for generating an address signal in response to a trailing edge of the address strobe signal, a clock signal generating means for generating a clock signal used for word line selection and an input signal for a next stage in response to a low level of the address strobe signal, and driving an inhibiting means for inhibiting / of the word line by the clock signal when the a address strobe signal is at/high level at a timing of a leading edge of the clock signal.
Claim 3
Dependent Claim
49 words
A clock signal generating circuit as claimed in claim 1, wherein said inhibiting means comprises an inverter for inverting the address strobe signal, and an AND gate for outputting a word line selection signal based on both high levels of the clock signal and the inverted address strobe signal.
Claim 4
Dependent Claim
67 words
A clock signal generating circuit as claimed in claim 1, wherein said inhibiting means comprises a producing a low level time out signal, in response to time out unit for the high level of the address strobe signal, during a predetermined period, and an AND gate for outputting a word line selection signal based on high levels of both the clock signal and inverted time out signal.
Claim 5
Dependent Claim
76 words
A clock signal generating circuit as claimed in claim 1, wherein said inhibiting means-comprises a producing a low level time out signal, in response to time out unit for / the high level or the address strobe signal, during a predetermined period, an AND gate for outputting the word line selection signal based on high levels of both the clock signal and the inverted time out signal, and an inverter for inverting the address strobe signal.
Claim 6
Dependent Claim
28 words
A clock signal generating circuit as claimed in claim 4, wherein said word line selection signal from the AND gate is fed back to the time out circuit.
Claim 7
Dependent Claim
22 words
A clock signal generating circuit as claimed any preceding in/claim wherein said active restore signal is fed back to the inhibiting means.
Claim 8
Dependent Claim
36 words
A clock signal generating circuit as claimed in any preceding claim, wherein said first drive level is a transistor-transistor logic (TTL) drive level, and said second drive level is a metal oxide semiconductor (MOS) drive level.
Claim 9
Dependent Claim
37 words
A clock signal generating circuit as claimed in any preceding claim, wherein said address buffer control means is also operable to generate an inverted address signal in response to a trailing edge of the address strobe signal.