Self-aligned split gate EPROM

Claim 2

An EPROM array containing a plurality of memory cells wherein each cell in the array includes a transistor containing a source region, a drain region, a channel region therebetween, and a floating gate formed over but insulated from a first portion of the channel region, characterized in that a first edge of the floating gate is aligned with and used to define one edge of the drain region and a second edge of the floating gate is over the channel region and separated from the closest edge of the source region by a second portion of the channel region, and a control gate formed over but insulated from the floating gate and formed over but insulated from the second portion of the channel region.

Claim 3

An EPROM array characterized by comprising a first plurality of memory cells, each memory cell including a transistor; a metal source contact line running in a first direction across the array; a multiplicity of source regions formed in silicon and running substantially parallel a selected distance across the array orthogonal to the metal source contact line; a contact between the metal source contact line and each of the underlying source regions thereby to allow a potential on the metal source contact line to be applied to each of the source regions; wherein each of the source regions serves as the source for at least 4N memory transistors, where N is a selected integer; a second plurality of metal bit lines running across the array substantially parallel to the metal source contact line, each metal bit line contacting the drain of a selected number of transistors in the array; a third plurality of control lines formed over the array orthogonal to the metal source contact line and the second plurality of metal bit lines; wherein each transistor in the array comprises a self-aligned split gate single transistor memory cell comprising a semiconductor substrate containing a source region and a drain region separated by a channel region; a floating gate formed over but insulated from a first portion of the channel region, a first edge of the floating gate being aligned with and used to define one edge of the drain region, a second edge of the floating gate being over the channel region and separated from the closest edge of the source region by a second portion of the channel region, and a control gate formed over but insulated from the floating edge and formed over but insulated from the second portion of the channel region; and wherein the control gate of each transistor comprises part of one of the third plurality of control lines formed over the top surface of the device.

Claim 4

An EPROM array characterized by comprising a first plurality of memory cells, each memory cell including a transistor; a metal source contact line running in a first direction across the array; a multiplicity of source regions formed in silicon and running substantially parallel a selected distance across the array orthogonal to the metal source contact line; a contact between the metal source contact line and each of the underlying source regions thereby to allow a potential on the metal source contact line to be applied to each of the source regions; wherein each of the source regions serves as the source for at least 4N memory transistors, where N is a selected integer; a second plurality of metal bit lines running across the array substantially parallel to the metal source contact line, each metal bit line contacting the drain of a selected number of transistors in the array; a third plurality of control lines formed over the array orthogonal to the metal source contact line and the second plurality of metal bit lines; wherein each transistor in the array comprises a self-aligned split gate single transistor memory cell comprising a semiconductor substrate containing a source region and a drain region separated by a channel region; a floating gate formed over but insulated from a first portion of the channel region, a first edge of the floating gate being aligned with and used to define one edge of the drain region, a second edge of the floating gate being over the channel region and separated from the closest edge of the source region by a second portion of the channel region, and a control gate formed over but insulated from the floating edge and formed over but insulated from the second portion of the channel region; and wherein the control gate of each transistor comprises part of one of the third plurality of control lines formed over the top surface of the device.

Claim 5

An EPROM array as claimed in claim 2 wherein each source region except the first and last serves as the source region for 4N transistors.

Claim 6

An EPROM array as claimed in claim 2 wherein each source region serves as the source region or at least 2N transistors.

Claim 7

An EPROM array as claimed in claim 2, 3 or 4 replicated M times to form an EPROM array with M times the memory cells of the structure of claim 2.

Claim 8

An EPROM array as claimed in any preceding claim wherein the control gate of each transistor extends over the second portion of the channel region to the source region and the edge of the control gate furthest from the floating gate is used to define, and is aligned with, the edge of the source region adjacent the channel region.