Mos integrated circuit having a protection circuit which includes divided protection resistors

Claim 2

A MOS integrated circuit comprising: a semiconductor substrate of one conductivity type; a circuit block including a plurality of MOS FET's formed in said semiconductor substrate; an input terminal formed on said semiconductor substrate; a plurality of well regions of the other conductivity type formed in said semiconductor substrate; a plurality of resistor regions of said one conductivity type, each of said resistor regions being formed in the corresponding one of said well regions; and means for connecting said resistor regions between said input terminal and said circuit block in series.

Claim 3

The MOS integrated circuit as claimed in claim 1, wherein the numbers of said well regions and said resistor regions are in a range between two and five.

Claim 4

The MOS integrated circuit as claimed in claim 1, wherein said circuit block includes P-channel MOS FET's and N-channel MOS FET's.

Claim 5

The MOS integrated circuit as claimed in claim 3, wherein said MOS integrated circuit further comprises first and second power supply terminals formed to supply a power to said circuit block, a first diode formed in said semiconductor substrate and connected between said first power supply terminal and a connecting point between the series connection of said resistor regions and said circuit block and a second diode formed in said semiconductor substrate and connected between said second power supply terminal and the connecting point between the series connection of said resistor and said circuit block.

Claim 6

The MOS integrated circuit as claimed in claim 4, wherein said well regions and said resistor regions are disposed in parallel, respectively.

Claim 7

The MOS integrated circuit as claimed in claim 4, wherein said well regions and said resistor regions are disposed in series, respectively.

Claim 8

A semiconductor device comprising: a semiconductor substrate of one conductivity type; a MOS field effect transistor formed in said semiconductor substrate and having a source, a drain and a gate; an input terminal formed on said semiconductor substrate; a plurality of first regions of the other conductivity type formed in said semiconductor substrate; a plurality of second regions of said one conductivity type formed to operate as diffusion resistors, each of said second regions being formed in each one of said first regions; and means for connecting said second regions between said input terminal and said gate of said MOS field effect transistor, said second regions being connected so as to operate as a series connection of said diffusion resistors.

Claim 9

A semiconductor device comprising: a semiconductor substrate of one conductivity type; a MOS field effect transistor formed in said semiconductor substrate and having a source, a drain and a gate; an input terminal formed on said semiconductor substrate; a plurality of first regions of the other conductivity type formed in said semiconductor substrate; a plurality of second regions of said one conductivity type formed to operate as diffusion resistors, each of said second regions being formed in each one of said first regions; and means for connecting said second regions between said input terminal and said gate of said MOS field effect transistor, said second regions being connected so as to operate as a series connection of said diffusion resistors.

Claim 10

The semiconductor device as claimed in claim 7, wherein the number of said first and second regions are respectively in a range between two and five.

Claim 11

The semiconductor device as claimed in claim 7, wherein said semiconductor device further comprises first and second power supply terminal formed on said semiconductor substrate, a first diode formed in said semiconductor substrate and connected between said gate of said MOS field effect transistor and said first power supply terminal, and a second diode formed in said semiconductor substrate and connected between said gate of said MOS field effect transistor and said second power supply terminal.

Claim 12

The semiconductor device as claimed in claim 9, wherein said MOS field effect transistor forms an electrical circuit together with other MOS field effect transistor formed in said semiconductor substrate.

Claim 13

The semiconductor device as claimed in claim 10, wherein said MOS field effect transistor and said other MOS field effect transistor are different channel types.